JTAG-HS1¶
The JTAG-HS1 programming cable is a high-speed programming solution for Xilinx® FPGAs. Official reference can be found here.
Configuration¶
You can configure debugging tool using debug_tool option in “platformio.ini” (Project Configuration File):
[env:myenv]
platform = ...
board = ...
debug_tool = digilent-hs1
If you would like to use this tool for firmware uploading, please change upload protocol:
[env:myenv]
platform = ...
board = ...
debug_tool = digilent-hs1
upload_protocol = digilent-hs1
More options:
Platforms¶
Name |
Description |
|---|---|
The CHIPS Alliance develops high-quality, open source hardware designs relevant to silicon devices and FPGAs. |
|
OpenHW Group is a not-for-profit, global organization that provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices. The OpenHW CV32E40P RISC-V core is the first open-source core for high-volume chips verified with the state-of-the-art process required for high-integrity, commercial SoCs. |
Frameworks¶
Name |
Description |
|---|---|
FreeRTOS is a real-time operating system kernel for embedded devices that has been ported to 40 microcontroller platforms |
|
Runtime Environment for Parallel Ultra Low Power platform targeting high energy efficiencies |
|
Software Development Kit for Parallel Ultra Low Power platform targeting high energy efficiencies |
|
The WD Firmware package contains firmware applications and Processor Support Package (PSP) for various cores, alongside demos which support all features |
|
The Zephyr Project is a scalable real-time operating system (RTOS) supporting multiple hardware architectures, optimized for resource constrained devices, and built with safety and security in mind |
Boards¶
Note
For more detailed board information please scroll tables below by horizontal.
Name |
Platform |
Debug |
MCU |
Frequency |
Flash |
RAM |
|---|---|---|---|---|---|---|
On-board |
320MHz |
16MB |
1.16MB |
|||
On-board |
320MHz |
16MB |
1.16MB |