OpenHW Group¶

Configuration:: platform = openhw

OpenHW Group is a not-for-profit, global organization that provides an infrastructure for hosting high quality open-source HW developments in line with industry best practices. The OpenHW CV32E40P RISC-V core is the first open-source core for high-volume chips verified with the state-of-the-art process required for high-integrity, commercial SoCs.

For more detailed information please visit vendor site.

Examples ¶

Examples are listed from OpenHW Group development platform repository:

Debugging ¶

Debugging - “1-click” solution for debugging with a zero configuration.

Tools & Debug Probes ¶

Supported debugging tools are listed in “Debug” column. For more detailed information, please scroll table by horizontal. You can switch between debugging Tools & Debug Probes using debug_tool option in “platformio.ini” (Project Configuration File).

Warning

You will need to install debug tool drivers depending on your system. Please click on compatible debug tool below for the further instructions.

On-Board Debug Tools ¶

Boards listed below have on-board debug probe and ARE READY for debugging! You do not need to use/buy external debug probe.

Name	MCU	Frequency	Flash	RAM
Digilent Nexys A7		320MHz	16MB	1.16MB

Stable and upstream versions ¶

You can switch between stable releases of OpenHW Group development platform and the latest upstream version using platform option in “platformio.ini” (Project Configuration File) as described below.

Stable¶

; Latest stable version
[env:latest_stable]
platform = openhw
board = ...

; Custom stable version
[env:custom_stable]
platform = openhw@x.y.z
board = ...

Upstream¶

[env:upstream_develop]
platform = https://github.com/platformio/platform-openhw.git
board = ...

Packages ¶

Name	Description
framework-pulp-runtime	Runtime Environment for Parallel Ultra Low Power platform
framework-pulp-sdk	Software Development Kit for Parallel Ultra Low Power platform
tool-openocd-riscv-pulp	Fork of Open On-Chip Debugger that has RISC-V support for PULP platform
tool-ovpsim-corev	Imperas RISC-V OVPsim CORE-V simulator provides a reference of the OpenHW Group CORE-V processor cores. The riscvOVPsim familiy of simulators implement the full and complete functionality of the RISC-V Foundation’s public User and Privilege specifications.
tool-renode	Renode is a development framework which accelerates IoT and embedded systems development by letting you simulate physical hardware systems
toolchain-riscv-pulp	GNU toolchain for RISC-V (PULP platform)

Warning

Linux Users:

Install “udev” rules 99-platformio-udev.rules

Raspberry Pi users, please read this article Enable serial port on Raspberry Pi.

Windows Users:

Please check that you have a correctly installed USB driver from board manufacturer

Frameworks ¶

Name	Description
PULP Runtime Environment	Runtime Environment for Parallel Ultra Low Power platform targeting high energy efficiencies
PULP SDK	Software Development Kit for Parallel Ultra Low Power platform targeting high energy efficiencies

Boards ¶

Note

You can list pre-configured boards by pio boards command or PlatformIO Boards Explorer
For more detailed board information please scroll the tables below by horizontally.

Digilent¶

Name	Debug	MCU	Frequency	Flash	RAM
Digilent Nexys A7	On-board		320MHz	16MB	1.16MB