Authors Edward Jones Jeremy Bennett Simon Cook
License CC-BY-SA-4.0
AAP: An Altruistic Processor
A reference Harvard architecture for
embedded compiler development
Simon Cook
Jeremy Bennett
Edward Jones
Application Note 13. Issue 2.1
Publication date December 2015
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Table of Contents
1. Introduction .................................................................................................................. 1
1.1. Revision History .................................................................................................. 1
2. Architecture Description ................................................................................................ 3
2.1. Basic architectural features ................................................................................ 3
2.2. Event Handling ................................................................................................... 5
2.3. NOP Behavior ....................................................................................................... 5
3. Instructions ................................................................................................................... 6
3.1. Notation .............................................................................................................. 6
3.1.1. Assembler Notation .................................................................................. 6
3.2. Instruction Format ............................................................................................. 6
3.3. Summary of Instructions .................................................................................... 8
3.3.1. 16-bit Instructions of AAP ........................................................................ 8
3.3.2. 32-bit Instructions of AAP ...................................................................... 10
3.4. Detailed Descriptions of 16-bit ALU Instructions .............................................. 14
3.4.1. NOP: No Operation ................................................................................. 14
3.4.2. ADD: Unsigned Add ............................................................................... 14
3.4.3. SUB: Unsigned Subtract ........................................................................ 14
3.4.4. AND: Bitwise AND .................................................................................. 15
3.4.5. OR: Bitwise OR ...................................................................................... 15
3.4.6. XOR: Bitwise Exclusive OR .................................................................... 15
3.4.7. ASR: Arithmetic Shift Right .................................................................... 16
3.4.8. LSL: Logical Shift Left ............................................................................ 16
3.4.9. LSR: Logical Shift Right ......................................................................... 17
3.4.10. MOV: Move Register to Register ............................................................ 17
3.4.11. ADDI: Unsigned Add Immediate ........................................................... 17
3.4.12. SUBI: Unsigned Subtract Immediate .................................................... 18
3.4.13. ASRI: Arithmetic Shift Right Immediate ................................................ 18
3.4.14. LSLI: Logical Shift Left Immediate ........................................................ 19
3.4.15. LSRI: Logical Shift Right Immediate ..................................................... 19
3.4.16. MOVI: Move Immediate to Register ....................................................... 20
3.5. Detailed Descriptions of 16-bit Load/Store Instructions .................................... 20
3.5.1. LDB: Indexed Load Byte ......................................................................... 20
3.5.2. LDW: Indexed Load Word ....................................................................... 20
3.5.3. LDB: Indexed Load Byte with Postincrement .......................................... 21
3.5.4. LDW: Indexed Load Word with Postincrement ........................................ 21
3.5.5. LDB: Indexed Load Byte with Predecrement ........................................... 22
3.5.6. LDW: Indexed Load Word with Predecrement ......................................... 22
3.5.7. STB: Indexed Store Byte ......................................................................... 23
3.5.8. STW: Indexed Store Word ....................................................................... 23
3.5.9. STB: Indexed Store Byte with Postincrement .......................................... 23
3.5.10. STW: Indexed Store Word with Postincrement ...................................... 24
3.5.11. STB: Indexed Store Byte with Predecrement ......................................... 24
3.5.12. STW: Indexed Store Word with Predecrement ....................................... 25
3.6. Detailed Descriptions of 16-bit Branch/Jump Instructions ............................... 25
3.6.1. BRA: Relative Branch ............................................................................. 25
3.6.2. BAL: Relative Branch and Link .............................................................. 26
3.6.3. BEQ: Relative Branch if Equal ............................................................... 26
3.6.4. BNE: Relative Branch if Not Equal ......................................................... 27
3.6.5. BLTS: Relative Branch if Signed Less Than ............................................ 27
3.6.6. BLES: Relative Branch if Signed Less Than or Equal To ......................... 28
3.6.7. BLTU: Relative Branch if Unsigned Less Than ........................................ 28
iii Copyright © 2015 Embecosm Limited
3.6.8. BLEU: Relative Branch if Unsigned Less Than or Equal To ..................... 28
3.6.9. JMP: Absolute Jump .............................................................................. 29
3.6.10. JAL: Absolute Jump and Link .............................................................. 29
3.6.11. JEQ: Absolute Jump if Equal ............................................................... 30
3.6.12. JNE: Absolute Jump if Not Equal ......................................................... 30
3.6.13. JLTS: Absolute Jump if Signed Less Than ............................................ 31
3.6.14. JLES: Absolute Jump if Signed Less Than or Equal To ......................... 31
3.6.15. JLTU: Absolute Jump if Unsigned Less Than ....................................... 31
3.6.16. JLEU: Absolute Jump if Unsigned Less Than or Equal To ..................... 32
3.7. Detailed Descriptions of 16-bit Miscellaneous Instructions ................................ 32
3.7.1. RTE: Return from Exception .................................................................. 32
3.8. Detailed Descriptions of 32-bit ALU Instructions .............................................. 33
3.8.1. NOP: No Operation ................................................................................. 33
3.8.2. ADD: Unsigned Add ............................................................................... 33
3.8.3. SUB: Unsigned Subtract ........................................................................ 34
3.8.4. AND: Bitwise AND .................................................................................. 34
3.8.5. OR: Bitwise OR ...................................................................................... 34
3.8.6. XOR: Bitwise Exclusive OR .................................................................... 35
3.8.7. ASR: Arithmetic Shift Right .................................................................... 35
3.8.8. LSL: Logical Shift Left ............................................................................ 36
3.8.9. LSR: Logical Shift Right ......................................................................... 36
3.8.10. MOV: Move Register to Register ............................................................ 37
3.8.11. ADDI: Unsigned Add Immediate ........................................................... 37
3.8.12. SUBI: Unsigned Subtract Immediate .................................................... 37
3.8.13. ASRI: Arithmetic Shift Right Immediate ................................................ 38
3.8.14. LSLI: Logical Shift Left Immediate ........................................................ 38
3.8.15. LSRI: Logical Shift Right Immediate ..................................................... 39
3.8.16. MOVI: Move Immediate to Register ....................................................... 39
3.8.17. ADDC: Unsigned Add with Carry .......................................................... 40
3.8.18. SUBC: Unsigned Subtract with Carry ................................................... 40
3.8.19. ANDI: Bitwise AND Immediate .............................................................. 41
3.8.20. ORI: Bitwise OR immediate .................................................................. 41
3.8.21. XORI: Bitwise Exclusive OR Immediate ................................................ 41
3.9. Detailed Descriptions of 32-bit Load/Store Instructions .................................... 42
3.9.1. LDB: Indexed Load Byte ......................................................................... 42
3.9.2. LDW: Indexed Load Word ....................................................................... 42
3.9.3. LDB: Indexed Load Byte with Postincrement .......................................... 43
3.9.4. LDW: Indexed Load Word with Postincrement ........................................ 43
3.9.5. LDB: Indexed Load Byte with Predecrement ........................................... 44
3.9.6. LDW: Indexed Load Word with Predecrement ......................................... 44
3.9.7. STB: Indexed Store Byte ......................................................................... 44
3.9.8. STW: Indexed Store Word ....................................................................... 45
3.9.9. STB: Indexed Store Byte with Postincrement .......................................... 45
3.9.10. STW: Indexed Store Word with Postincrement ...................................... 46
3.9.11. STB: Indexed Store Byte with Predecrement ......................................... 46
3.9.12. STW: Indexed Store Word with Predecrement ....................................... 47
3.10. Detailed Descriptions of 32-bit Branch/Jump Instructions ............................. 47
3.10.1. BRA: Relative Branch ........................................................................... 47
3.10.2. BAL: Relative Branch and Link ............................................................ 48
3.10.3. BEQ: Relative Branch if Equal ............................................................. 48
3.10.4. BNE: Relative Branch if Not Equal ....................................................... 49
3.10.5. BLTS: Relative Branch if Signed Less Than .......................................... 49
3.10.6. BLES: Relative Branch if Signed Less Than or Equal To ........................ 50
iv Copyright © 2015 Embecosm Limited
3.10.7. BLTU: Relative Branch if Unsigned Less Than ...................................... 50
3.10.8. BLEU: Relative Branch if Unsigned Less Than or Equal To ................... 51
3.10.9. JMP: Absolute Jump ............................................................................ 51
3.10.10. JAL: Absolute Jump and Link ............................................................ 52
3.10.11. JEQ: Absolute Jump if Equal ............................................................. 52
3.10.12. JNE: Absolute Jump if Not Equal ....................................................... 52
3.10.13. JLTS: Absolute Jump if Signed Less Than .......................................... 53
3.10.14. JLES: Absolute Jump if Signed Less Than or Equal To ....................... 53
3.10.15. JLTU: Absolute Jump if Unsigned Less Than ...................................... 54
3.10.16. JLEU: Absolute Jump if Unsigned Less Than or Equal To ................... 54
3.10.17. JMPL: Absolute Jump Long ................................................................ 55
3.10.18. JALL: Absolute Jump Long and Link .................................................. 55
3.10.19. JEQL: Absolute Jump Long if Equal ................................................... 56
3.10.20. JNEL: Absolute Jump Long if Not Equal ............................................. 56
3.10.21. JLTSL: Absolute Jump Long if Signed Less Than ................................ 57
3.10.22. JLESL: Absolute Jump Long if Signed Less Than or Equal To ............. 57
3.10.23. JLTUL: Absolute Jump Long if Unsigned Less Than ........................... 58
3.10.24. JLEUL: Absolute Jump Long if Unsigned Less Than or Equal To ......... 58
3.11. Detailed Descriptions of 32-bit Miscellaneous Instructions .............................. 59
4. ABI .............................................................................................................................. 60
4.1. Defined Registers .............................................................................................. 60
4.2. Calling Convention ............................................................................................ 60
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List of Figures
2.1. AAP architecture ........................................................................................................ 3
3.1. AAP 16-bit instruction formats. .................................................................................. 7
3.2. AAP 32-bit instruction formats. .................................................................................. 8
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List of Tables
3.1. 16-bit ALU instructions .............................................................................................. 8
3.2. 16-bit load/store instructions .................................................................................... 9
3.3. 16-bit branch/jump instructions ............................................................................... 9
3.4. Miscellaneous 16-bit instructions ............................................................................. 10
3.5. 32-bit ALU instructions ............................................................................................ 10
3.6. 32-bit load/store instructions .................................................................................. 11
3.7. 32-bit branch/jump instructions .............................................................................. 12
vii Copyright © 2015 Embecosm Limited
Chapter 1. Introduction
AAP is a Harvard architecture specification designed for experimenting with various features
in compiler back ends. In particular it has features that are common within small deeply
embedded systems, such as a dearth of registers, word address code memory and pointers
that will not fit in an integer.
It is also designed to be easy to use in demonstrations and education/training. This includes
hardware and simulator implementation as well as the tool chain and library implementation.
The design is based on no processor in particular, although as an open hardware design, it is
inspired by the OpenRISC and RISC-V projects. There are features drawn from a wide range
of processors developed over the past 30 years. Indeed the branch-and-link operation goes
back even further, to the IBM 360.
1.1. Revision History
Revision History
Revision 2.1 10 December 2015 Edward Jones
The Postincrement and Predecrement store instructions defined Ra rather than Rd as the
operand to which the update was applied.
Postincrement, Predecement instructions now increment or decrement by the amount of the
provided offset (Previously it was a fixed offset of one or two bytes for byte and word operations
respectively).
BGTS, BGTU, JGTS, JGTU, JGTSL, JGTUL. These instructions have been replaced with branches
with a 'Less Than or Equal To' condition. The new instructions are BLES, BLEU, JLES, JLEU,
JLESL, JLEUL.
Revision 2.0 9 October 2015 Jeremy Bennett
Issue 2.0, which covers the entire ISA.
Revision 1.9 8 October 2015 Jeremy Bennett
Final draft before release 2.0. Adds some notation description and a chapter for the
architecture description, which incorporates some of the old intro and the old chapter on NOP
side effects.
Revision 1.8 8 October 2015 Jeremy Bennett
All 32-bit instructions described.
Revision 1.7 8 September 2015 Jeremy Bennett
First batch of 32-bit ALU instruction described. Various typos fixed.
Revision 1.6 8 September 2015 Jeremy Bennett
All 16-bit instructions described. Encoding of JAL corrected in the summary. Rb used to store
the PC for all BAL and JAL instructions.
Revision 1.5 8 September 2015 Jeremy Bennett
16-bit ALU instruction details complete. Change opcode mnemonics for ALU instructions with
constant arguments. Off-by-one encoding for immediate shift values described.
Revision 1.4 4 September 2015 Jeremy Bennett
Structure of detailed instruction descriptions refined. Most 16-bit ALU instructions now
documented.
Revision 1.3 4 September 2015 Jeremy Bennett
All instruction formats now shown. All summaries in new format.
Revision 1.2 3 September 2015 Jeremy Bennett
First stage of improved formatting, using LibreOffice Impress to as the basis of the instruction
format diagrams for 32-bit instructions (generating SVG and PNG). Clearer summary of
instructions used for 32-bit ALU instructions.
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Revision 1.1 18 July 2015 Jeremy Bennett
Start of revision process. Remove load/store double instructions. Use second opcode field of
32-bit load/store as extra constant field. Make all load/store offsets signed. Make BAL use Rb
rather than Ra to keep constant field contiguous.
Revision 1.0 14 April 2015 Jeremy Bennett
Bump release number to 1.0 for issue.
Revision 0.9 14 April 2015 Jeremy Bennett
First public release outlining the architecture.
Revision N/A 11 April 2015 Jeremy Bennett
Correct encoding of 32-bit branches (4 more bits of offset). Correct NOP constant meanings.
Matches server/simulator commit b179463.
Revision N/A 8 April 2015 Jeremy Bennett
Full summary of all 16-bit and 32-bit instructions.
Revision N/A 8 April 2015 Jeremy Bennett
Updated preface in preparation for revised architecture.
Revision N/A 6 April 2015 Simon Cook
Initial concept
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Chapter 2. Architecture Description
Figure 2.1 shows the overall structure of AAP.
Code Memories(words)
4 - 64 Registers
R0 0 x FFFFFF
R3
R4
R6 3 0x0000
STATUS/PC Data Memories (bytes)
0 x FFFF
ALU
0x0000
Figure 2.1. AAP architecture
2.1. Basic architectural features
These are the key features of the AAP design.
16-bit RISC The core design sticks to the RISC principles of 3-address register-
architecture to-register operation, a small number of operations and a simple to
implement data path. The fundamental data type is the 16-bit integer.
Configurable number Although 32/64-bit RISC architectures typically have 16 or more
of registers general purpose registers, small deeply embedded processors often
have far fewer. This represents a significant compiler implementation
challenge. To allow exploration of this area, AAP can be configured
with between 4 and 64 16-bit registers.
Harvard memory The basic architecture provides a 64k byte addressed data memory
layout and a separate 16M word instruction memory. By requiring more
than 16-bits to address the instruction memory, the compiler writer
can explore the challenge of pointers which are larger than the native
integer type.
Deeply embedded systems often have very small memories,
particularly for data, so the size of memories can be configured.
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Many architectures also provide more than two address spaces, often
for special purposes. For example a small EEPROM alongside Flash
memory, or the Special Purpose Register block of OpenRISC. AAP
can support additional address spaces, allowing support for multiple
address spaces throughout the tool chain to be explored.
24-bit program AAP requires a 24-bit program counter, which is held in a 32-bit
counter with 8-bit register. The top bits of the program counter then form a status
status register register. Jump instructions ignore these top 8 bits.
At present only one status bit is defined, a carry flag to allow multiple
precision arithmetic.
16/32-bit A frequent feature of many architectures is to provide a subset of the
instruction encoding most commonly used parts of the Instruction Set Architecture (ISA)
in a short encoding of 16-bits. Less common instructions are then
encoded in 32-bits.
Optimizing to use these shorter instructions, is particularly
important for compilers for embedded targets, where memory is at a
premium. AAP provides such a 16-bit subset with a 32-bit encoding
of the full ISA. However it follows the instruction chaining of RISC-V,
so even longer instructions could be created in the future.
The fields within each 16-bit instruction are fixed. A 32-bit
instruction pairs up those fields to increase the number of
instructions.
3-address code AAP has stuck rigidly to the RISC principle of 3-address instructions
throughout. Almost all instructions come in two variants, one where
the third argument is a register, and one where the third argument
is a constant.
No flags for flow of There are no flag registers indicating the results of operations for use
control in conditional jumps. Instead the operation is encoded within the
jump instruction itself.
There is an 8-bit status register as part of the program counter, which
includes a carry flag. However this is not used for flow-of-control, but
to enable multiple precision arithmetic.
Little endian The architecture is little-endian—the least significant byte of a word
or double word is at the lowest address.
The behavior for instruction memory is that one word is fetched, since
it may be a 16-bit instruction. If a second word is needed, then its
fields are paired with the first instructions to give larger values for
each field. This is done in little-endian fashion, i.e. the field from the
second instruction forms the most significant bits of the combined
field.
No delay slots Early RISC designs introduced the concept of a delay slot after
branches. This avoided pipeline delays in branch processing.
Implementations can now avoid such pipeline delay, so like most
modern architectures, AAP does not have delay slots.
NOP with argument This idea is taken from OpenRISC. The NOP opcode includes fields to
for simulator control specify a register and a constant. These can be used in both hardware
and simulation to trigger side-effects.
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2.2. Event Handling
Events indirect through instructions in the first 256 (0x100) words of instruction memory.
In general these should be 32-bit branch instructions, which means event handlers should
reside in first or last 221 words of instruction memory.
At present the following event vector locations (word addresses) are defined
0x00 Power-on reset.
0x02 Bus error
The event handling mechanism is still in development. In particular no location is yet defined
for the return address to be used by the RTE instruction (see Section 3.7.1).
2.3. NOP Behavior
The NOP instruction takes an immediate argument which can be used to trigger certain
behavior in a simulator.
• 0 : Breakpoint
• 1 : Do nothing
• 2 : Exit with return code in Rd
• 3 : Write char in Rd to standard output.
• 4 : Write char in Rd to standard error.
• All other values: do nothing, but future behavior not guaranteed.
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Chapter 3. Instructions
3.1. Notation
In the instruction descriptions below, the following notation is used.
Rd Destination register number "d" in the general registers.
Ra First source register number "a" in the general registers.
Rb Second source register number "b" in the general registers.
PC The program counter
I Unsigned immediate value
S Signed immediate value
dmem[i] Byte offset "i" in the data memory.
imem[i] Word offset "i" in the code memory.
carry The carry flag.
SignExt(x) The value "x" (which may be one of the above) sign extended as necessary.
Individual bits in the encodings are used as follows.
0 A zero bit.
1 A one bit.
dn Bit "n" of the destination register field.
an Bit "n" of the the first source register field.
bn Bit "n" of the the second source register field.
in Bit "n" of the the unsigned constant field.
sn Bit "n" of the the signed constant field.
3.1.1. Assembler Notation
The assembler generally follows standard GNU assembler conventions. Instructions take the
following form:
[label:] opcode [arguments]
There may be up to 3 arguments, separated by commas. Registers are indicted by R followed
by a number. Constants and constant expressions may be preceded by # for clarity, but this
is not required. C style notation to indicate the base of constants, which defaults to decimal.
3.2. Instruction Format
The 16-bit instruction formats are shown in Figure 3.1 and the 32-bit instruction formats in
Figure 3.2.
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Format
1 0 c1 c0 o3 o2 o1 o0 d2 d1 d0 a2 a1 a0 b2 b1 b0
2 0 c1 c0 o3 o2 o1 o0 d2 d1 d0 a2 a1 a0 i2 i1 i0
3 0 c1 c0 o3 o2 o1 o0 s2 s1 s0 a2 a1 a0 b2 b1 b0
4 0 c1 c0 o3 o2 o1 o0 d2 d1 d0 a2 a1 a0 s2 s1 s0
5 0 c 1 c 0 o 3 o 2 o 1 o 0 d2 d1 d0 i 5 i 4 i 3 i 2 i 1 i 0
6 0 c 1 c 0 o 3 o 2 o 1 o 0 s 5 s 4 s 3 s 2 s 1 s 0 b2 b1 b0
7 0 c1 c0 o 3 o 2 o 1 o 0 s8 s7 s6 s5 s4 s3 s2 s1 s0
c 1c 0 Opcode class b2...b0 Second source register
o3...o0 Opcode in...i0 Unsigned immediate
d2...d0 Destination register sn...s0 Unsigned immediate
a2...a0 First source register
Figure 3.1. AAP 16-bit instruction formats.
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Format First word (low address) Second word (high address)
8 1 c1 c0 o3 o2 o1 o0 d2 d1 d0 a2 a1 a0 b2 b1 b0 0 c3 c2 o7 o6 o5 o4 d5 d4 d3 a5 a4 a3 b5 b4 b3
9 1 c1 c0 o3 o2 o1 o0 d2 d1 d0 a2 a1 a0 i2 i1 i0 0 c3 c2 o6 o5 o4 0 d5 d4 d3 a5 a4 a3 i5 i4 i3
10 1 c1 c0 o3 o2 o1 o0 d2 d1 d0 a2 a1 a0 i2 i1 i0 0 c3 c2 i8 i7 i6 1 d5 d4 d3 a5 a4 a3 i5 i4 i3
11 1 c1 c0 o3 o2 o1 o0 d2 d1 d0 a2 a1 a0 i2 i1 i0 0 c3 c2 i9 i8 i7 i6 d5 d4 d3 a5 a4 a3 i5 i4 i3
12 1 c1 c0 o3 o2 o1 o0 s2 s1 s0 a2 a1 a0 b2 b1 b0 0 c3 c2 s9 s8 s7 s6 s5 s4 s3 a5 a4 a3 b5 b4 b3
13 1 c1 c0 o3 o2 o1 o0 d2 d1 d0 a2 a1 a0 s2 s1 s0 0 c3 c2 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
14 1 c1 c0 o3 o2 o1 o0 d2 d1 d0 i5 i4 i3 i2 i1 i0 0 c3 c2 o7 o6 o5 o4 d5 d4 d3i11i10 i9 i8 i7 i6
15 1 c1 c0 o3 o2 o1 o0 d2 d1 d0 i5 i4 i3 i2 i1 i0 0 c3 c2 i15i14i13i12d5 d4 d3i11i10 i9 i8 i7 i6
16 1 c1 c0 o3 o2 o1 o0 s5 s4 s3 s2 s1 s0 b2 b1 b0 0 c3 c2s15s14s13s12s11s10s9 s8 s7 s6 b5 b4 b3
17 1 c1 c0 o3 o2 o1 o0 s8 s7 s6 s5 s4 s3 s2 s1 s0 0 c3 c2s21s20s19s18s17s16s15s14s13s12s11s10s9
c3...c0 Opcode class b5...b0 Second source register
on...o0 Opcode in...i0 Unsigned immediate
d5...d0 Destination register sn...s0 Unsigned immediate
a5...a0 First source register
Figure 3.2. AAP 32-bit instruction formats.
Longer instruction formats are possible by setting the top bit of the second word to 1. By
repeating this, instructions of arbitrary length are possible.
3.3. Summary of Instructions
3.3.1. 16-bit Instructions of AAP
• Table 3.1 lists all the 16-bit ALU instructions, which have class 00;
• Table 3.2 lists all the 16-bit load/store instructions, which have class 01;
• Table 3.3 lists all the 16-bit branch/jump instructions, which have class 10; and
• Table 3.4 lists all the 16-bit miscellaneous instructions, which have class 11.
Opcode Format Encoding Description
NOP Rd,I 5 0000000dddiiiiii No operation
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Opcode Format Encoding Description
ADD Rd,Ra,Rb 1 0000001dddaaabbb Unsigned add
SUB Rd,Ra,Rb 1 0000010dddaaabbb Unsigned subtract
AND Rd,Ra,Rb 1 0000011dddaaabbb Bitwise AND
OR Rd,Ra,Rb 1 0000100dddaaabbb Bitwise OR
XOR Rd,Ra,Rb 1 0000101dddaaabbb Bitwise exclusive OR
ASR Rd,Ra,Rb 1 0000110dddaaabbb Arithmetic shift right
LSL Rd,Ra,Rb 1 0000111dddaaabbb Logical shift left
LSR Rd,Ra,Rb 1 0001000dddaaabbb Logical shift right
MOV Rd,Ra 1 0001001dddaaa000 Move register to register
ADDI Rd,Ra,#I 2 0001010dddaaaiii Unsigned add immediate
SUBI Rd,Ra,#I 2 0001011dddaaaiii Unsigned subtract immediate
ASRI Rd,Ra,#I 2 0001100dddaaaiii Arithmetic shift right immediate
LSLI Rd,Ra,#I 2 0001101dddaaaiii Logical shift left immediate
LSRI Rd,Ra,#I 2 0001110dddaaaiii Logical shift right immediate
MOVI Rd,#I 5 0001111dddiiiiii Move immediate to register
Table 3.1. 16-bit ALU instructions
Opcode Format Encoding Description
LDB Rd,(Ra,S) 4 0010000dddaaasss Indexed load byte
LDW Rd,(Ra,S) 4 0010100dddaaasss Indexed load word
LDB Rd,(Ra+,S) 4 0010001dddaaasss Indexed load byte with postincrement
LDW Rd,(Ra+,S) 4 0010101dddaaasss Indexed load word with postincrement
LDB Rd,(-Ra,S) 4 0010010dddaaasss Indexed load byte with predecrement
LDW Rd,(-Ra,S) 4 0010110dddaaasss Indexed load word with predecrement
STB (Rd,S),Ra 4 0011000dddaaasss Indexed store byte
STW (Rd,S),Ra 4 0011100dddaaasss Indexed store word
STB (Rd+,S),Ra 4 0011001dddaaasss Indexed store byte with postincrement
STW (Rd+,S),Ra 4 0011101dddaaasss Indexed store word with postincrement
STB (-Rd,S),Ra 4 0011010dddaaasss Indexed store byte with predecrement
STW (-Rd,S),Ra 4 0011110dddaaasss Indexed store word with predecrement
Table 3.2. 16-bit load/store instructions
Opcode Format Encoding Description
BRA S 7 0100000sssssssss Relative branch
BAL S,Rb 6 0100001ssssssbbb Relative branch and link
BEQ S,Ra,Rb 3 0100010sssaaabbb Relative branch if equal
BNE S,Ra,Rb 3 0100011sssaaabbb Relative branch if not equal
BLTS S,Ra,Rb 3 0100100sssaaabbb Relative branch if signed less than
9 Copyright © 2015 Embecosm Limited
Opcode Format Encoding Description
Relative branch if signed less than or
BLES S,Ra,Rb 3 0100101sssaaabbb
equal to
BLTU S,Ra,Rb 3 0100110sssaaabbb Relative branch if unsigned less than
Relative branch if unsigned less than or
BLEU S,Ra,Rb 3 0100111sssaaabbb
equal to
JMP Rd 1 0101000ddd000000 Absolute jump
JAL Rd,Rb 1 0101001ddd000bbb Absolute jump and link
JEQ Rd,Ra,Rb 1 0101010dddaaabbb Absolute jump if equal
JNE Rd,Ra,Rb 1 0101011dddaaabbb Absolute jump if not equal
JLTS Rd,Ra,Rb 1 0101100dddaaabbb Absolute jump if signed less than
Absolute jump if signed less than or
JLES Rd,Ra,Rb 1 0101101dddaaabbb
equal to
JLTU Rd,Ra,Rb 1 0101110dddaaabbb Absolute jump if unsigned less than
Absolute jump if unsigned less than or
JLEU Rd,Ra,Rb 1 0101111dddaaabbb
equal to
Table 3.3. 16-bit branch/jump instructions
Opcode Format Encoding Description
RTE Rd 1 0110000ddd000000 Return from exception
Table 3.4. Miscellaneous 16-bit instructions
3.3.2. 32-bit Instructions of AAP
In the following list, the encoding is shown with the word at the lower address first.
• Table 3.5 lists all the 32-bit ALU instructions, which have class 00xx;
• Table 3.6 lists all the 32-bit load/store instructions, which have class 01xx;
• Table 3.7 lists all the 32-bit branch/jump instructions, which have class 10xx; and
• There are no 32-bit instructions in the miscellaneous class, but if there were, they would
have have class 11xx.
Opcode Format Encoding Description
1000000dddiiiiii
NOP Rd,I 14 No operation
0000000dddiiiiii
1000001dddaaabbb
ADD Rd,Ra,Rb 8 Unsigned add
0000000dddaaabbb
1000010dddaaabbb
SUB Rd,Ra,Rb 8 Unsigned subtract
0000000dddaaabbb
1000011dddaaabbb
AND Rd,Ra,Rb 8 Bitwise AND
0000000dddaaabbb
1000100dddaaabbb
OR Rd,Ra,Rb 8 Bitwise OR
0000000dddaaabbb
10 Copyright © 2015 Embecosm Limited
Opcode Format Encoding Description
1000101dddaaabbb
XOR Rd,Ra,Rb 8 Bitwise exclusive OR
0000000dddaaabbb
1000110dddaaabbb
ASR Rd,Ra,Rb 8 Arithmetic shift right
0000000dddaaabbb
1000111dddaaabbb
LSL Rd,Ra,Rb 8 Logical shift left
0000000dddaaabbb
1001000dddaaabbb
LSR Rd,Ra,Rb 8 Logical shift right
0000000dddaaabbb
1001001dddaaa000
MOV Rd,Ra 8 Move register to register
0000000dddaaa000
1001010dddaaaiii
ADDI Rd,Ra,I 11 Unsigned add immediate
000iiiidddaaaiii
1001011dddaaaiii
SUBI Rd,Ra,I 11 Unsigned subtract immediate
000iiiidddaaaiii
1001100dddaaaiii
ASRI Rd,Ra,I 9 Arithmetic shift right immediate
0000000dddaaaiii
1001101dddaaaiii
LSLI Rd,Ra,I 9 Logical shift left immediate
0000000dddaaaiii
1001110dddaaaiii
LSRI Rd,Ra,I 9 Logical shift right immediate
0000000dddaaaiii
1001111dddiiiiii
MOVI Rd,I 15 Move immediate to register
000iiiidddiiiiii
1000001dddaaabbb
ADDC Rd,Ra,Rb 8 Add with carry
0000001dddaaabbb
1000010dddaaabbb
SUBC Rd,Ra,Rb 8 Subtract with carry
0000001dddaaabbb
1000011dddaaaiii
ANDI Rd,Ra,I 10 Bitwise AND immediate
000iii1dddaaaiii
1000100dddaaaiii
ORI Rd,Ra,I 10 Bitwise OR immediate
000iii1dddaaaiii
1000101dddaaaiii
XORI Rd,Ra,I 10 Bitwise exclusive OR immediate
000iii1dddaaaiii
Table 3.5. 32-bit ALU instructions
Opcode Format Encoding Description
1010000dddaaasss
LDB Rd,(Ra,S) 13 Indexed load byte
000ssssdddaaasss
11 Copyright © 2015 Embecosm Limited
Opcode Format Encoding Description
1010100dddaaasss
LDW Rd,(Ra,S) 13 Indexed load word
000ssssdddaaasss
1010001dddaaasss
LDB Rd,(Ra+,S) 13 Indexed load byte with postincrement
000ssssdddaaasss
1010101dddaaasss
LDW Rd,(Ra+,S) 13 Indexed load word with postincrement
000ssssdddaaasss
1010010dddaaasss
LDB Rd,(-Ra,S) 13 Indexed load byte with predecrement
000ssssdddaaasss
1010110dddaaasss
LDW Rd,(-Ra,S) 13 Indexed load word with predecrement
000ssssdddaaasss
1011000dddaaasss
STB (Rd,S),Ra 13 Indexed store byte
000ssssdddaaasss
1011100dddaaasss
STW (Rd,S),Ra 13 Indexed store word
000ssssdddaaasss
1011001dddaaasss
STB (Rd+,S),Ra 13 Indexed store byte with postincrement
000ssssdddaaasss
1011101dddaaasss
STW (Rd+,S),Ra 13 Indexed store word with postincrement
000ssssdddaaasss
1011010dddaaasss
STB (-Rd,S),Ra 13 Indexed store byte with predecrement
000ssssdddaaasss
1011111dddaaasss
STW (-Rd,S),Ra 13 Indexed store word with predecrement
000ssssdddaaasss
Table 3.6. 32-bit load/store instructions
Opcode Format Encoding Description
1100000sssssssss
BRA S 17 Relative branch
000sssssssssssss
1100001ssssssbbb
BAL S,Rb 16 Relative branch and link
000ssssssssssbbb
1100010sssaaabbb
BEQ S,Ra,Rb 12 Relative branch if equal
000sssssssaaabbb
1100011sssaaabbb
BNE S,Ra,Rb 12 Relative branch if not equal
000sssssssaaabbb
1100100sssaaabbb
BLTS S,Ra,Rb 12 Relative branch if signed less than
000sssssssaaabbb
1100101sssaaabbb Relative branch if signed less than or
BLES S,Ra,Rb 12
000sssssssaaabbb equal to
12 Copyright © 2015 Embecosm Limited
Opcode Format Encoding Description
1100110sssaaabbb
BLTU S,Ra,Rb 12 Relative branch if unsigned less than
000sssssssaaabbb
1100111sssaaabbb Relative branch if unsigned less than or
BLEU S,Ra,Rb 12
000sssssssaaabbb equal to
1101000ddd000000
JMP Rd 8 Absolute jump
0000000ddd000000
1101001ddd000bbb
JAL Rd,Rb 8 Absolute jump and link
0000000ddd000bbb
1101010dddaaabbb
JEQ Rd,Ra,Rb 8 Absolute jump if equal
0000000dddaaabbb
1101011dddaaabbb
JNE Rd,Ra,Rb 8 Absolute jump if not equal
0000000dddaaabbb
1101100dddaaabbb
JLTS Rd,Ra,Rb 8 Absolute jump if signed less than
0000000dddaaabbb
1101101dddaaabbb Absolute jump if signed less than or
JLES Rd,Ra,Rb 8
0000000dddaaabbb equal to
1101110dddaaabbb
JLTU Rd,Ra,Rb 8 Absolute jump if unsigned less than
0000000dddaaabbb
1101111dddaaabbb Absolute jump if unsigned less than or
JLEU Rd,Ra,Rb 8
0000000dddaaabbb equal to
1101000ddd000000
JMPL Rd 8 Absolute jump long
0000001ddd000000
1101001ddd000bbb
JALL Rd,Rb 8 Absolute jump long and link
0000001ddd000bbb
1101010dddaaabbb
JEQL Rd,Ra,Rb 8 Absolute jump long if equal
0000001dddaaabbb
1101011dddaaabbb
JNEL Rd,Ra,Rb 8 Absolute jump long if not equal
0000001dddaaabbb
1101100dddaaabbb
JLTSL Rd,Ra,Rb 8 Absolute jump long if signed less than
0000001dddaaabbb
1101101dddaaabbb Absolute jump long if signed less than
JLESL Rd,Ra,Rb 8
0000001dddaaabbb or equal to
1101110dddaaabbb Absolute jump long if unsigned less
JLTUL Rd,Ra,Rb 8
0000001dddaaabbb than
1101111dddaaabbb Absolute jump long if unsigned less
JLEUL Rd,Ra,Rb 8
0000001dddaaabbb than or equal to
Table 3.7. 32-bit branch/jump instructions
13 Copyright © 2015 Embecosm Limited
3.4. Detailed Descriptions of 16-bit ALU Instructions
3.4.1. NOP: No Operation
Encoding (format 5):
0 0 0 0 0 0 0 d 2 d 1 d 0 i5 i4 i3 i2 i1 i0
Syntax:
NOP Rd,I
Constraints:
d≤7
I ≤ 63
Outcome:
PC ← PC + 1
Notes:
This opcode may trigger side-effects in implementations, depending on the value of I,
particularly when simulating (see Section 2.3).
All implementations should use d = 0, I = 0 as the break instruction for debugging, which
should halt the processor.
All implementations should use d = 0, I = 1 as a true no-operation instruction.
The rationale behind this decision is that in an erroneous program, the most likely value
to be encountered as a random instruction is zero, which will stop the processor.
3.4.2. ADD: Unsigned Add
Encoding (format 1):
0 0 0 0 0 0 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
ADD Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
Rd ← R a + R b
carry ← ( ( Ra + Rb ) ≥ 216 ) ? 1 : 0
PC ← PC + 1
3.4.3. SUB: Unsigned Subtract
Encoding (format 1):
0 0 0 0 0 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
14 Copyright © 2015 Embecosm Limited
SUB Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
Rd ← Ra - Rb
carry ← ( Rb > Ra ) ? 1 : 0
PC ← PC + 1
3.4.4. AND: Bitwise AND
Encoding (format 1):
0 0 0 0 0 1 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
AND Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
Rd ← Ra & Rb
PC ← PC + 1
3.4.5. OR: Bitwise OR
Encoding (format 1):
0 0 0 0 1 0 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
OR Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
Rd ← R a | R b
PC ← PC + 1
3.4.6. XOR: Bitwise Exclusive OR
Encoding (format 1):
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0 0 0 0 1 0 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
XOR Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
Rd ← R a ^ R b
PC ← PC + 1
3.4.7. ASR: Arithmetic Shift Right
Encoding (format 1):
0 0 0 0 1 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
ASR Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
Rd ← ( Ra | ( carry << 16 ) ) >> Rb )
carry ← 0
PC ← PC + 1
Notes:
If Rb ≥ 17 the result in Rd will be zero.
The carry flag is always cleared, even if a shift of zero is specified.
3.4.8. LSL: Logical Shift Left
Encoding (format 1):
0 0 0 0 1 1 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
LSL Rd,Ra,Rb
Constraints:
a≤7
b≤7
16 Copyright © 2015 Embecosm Limited
d≤7
Outcome:
Rd ← Ra << Rb
PC ← PC + 1
Notes:
If Rb ≥ 16 the result in Rd will be zero.
3.4.9. LSR: Logical Shift Right
Encoding (format 1):
0 0 0 1 0 0 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
LSR Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
Rd ← Ra >> Rb
PC ← PC + 1
Notes:
If Rb ≥ 16 the result in Rd will be zero.
3.4.10. MOV: Move Register to Register
Encoding (format 1):
0 0 0 1 0 0 1 d2 d1 d0 a2 a1 a0 0 0 0
Syntax:
MOV Rd,Ra
Constraints:
a≤7
d≤7
Outcome:
Rd ← R a
PC ← PC + 1
3.4.11. ADDI: Unsigned Add Immediate
Encoding (format 2):
0 0 0 1 0 1 0 d2 d1 d0 a2 a1 a0 i2 i1 i0
17 Copyright © 2015 Embecosm Limited
Syntax:
ADDI Rd,Ra,I
Constraints:
a≤7
d≤7
I≤7
Outcome:
Rd ← R a + I
carry ← ( ( Ra + I ) ≥ 216 ) ? 1 : 0
PC ← PC + 1
Notes:
Adding constant zero can be used to clear the carry flag.
3.4.12. SUBI: Unsigned Subtract Immediate
Encoding (format 2):
0 0 0 1 0 1 1 d2 d1 d0 a2 a1 a0 i2 i1 i0
Syntax:
SUBI Rd,Ra,I
Constraints:
a≤7
d≤7
I≤7
Outcome:
Rd ← R a - I
carry ← ( I > Ra ) ? 1 : 0
PC ← PC + 1
3.4.13. ASRI: Arithmetic Shift Right Immediate
Encoding (format 2):
0 0 0 1 1 0 0 d2 d1 d0 a2 a1 a0 i2 i1 i0
Syntax:
ASRI Rd,Ra,I
Constraints:
a≤7
d≤7
1≤I≤8
Outcome:
18 Copyright © 2015 Embecosm Limited
Rd ← ( Ra | ( carry << 16 ) ) >> I )
carry ← 0
PC ← PC + 1
Notes:
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 0002.
The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag,
since there are other ways of clearing the it (for example adding constant zero).
3.4.14. LSLI: Logical Shift Left Immediate
Encoding (format 2):
0 0 0 1 1 0 1 d2 d1 d0 a2 a1 a0 i2 i1 i0
Syntax:
LSLI Rd,Ra,I
Constraints:
a≤7
d≤7
1≤I≤8
Outcome:
Rd ← Ra << I
PC ← PC + 1
Notes:
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 0002.
The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag,
since there are other ways of clearing the it (for example adding constant zero).
3.4.15. LSRI: Logical Shift Right Immediate
Encoding (format 2):
0 0 0 1 1 1 0 d2 d1 d0 a2 a1 a0 i2 i1 i0
Syntax:
LSRI Rd,Ra,I
Constraints:
a≤7
d≤7
1≤I≤8
Outcome:
Rd ← Ra >> I
PC ← PC + 1
Notes:
19 Copyright © 2015 Embecosm Limited
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as 0002.
The rationale is that shifting by zero is pointless. It is not needed to clear the carry flag,
since there are other ways of clearing the it (for example adding constant zero).
3.4.16. MOVI: Move Immediate to Register
Encoding (format 5):
0 0 0 1 1 1 1 d 2 d 1 d 0 i5 i4 i3 i2 i1 i0
Syntax:
MOVI Rd,I
Constraints:
d≤7
I ≤ 63
Outcome:
Rd ← I
PC ← PC + 1
3.5. Detailed Descriptions of 16-bit Load/Store Instructions
3.5.1. LDB: Indexed Load Byte
Encoding (format 4):
0 0 1 0 0 0 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
LDB Rd,(Ra,S)
Constraints:
d≤7
-4 ≤ S ≤ 3
Outcome:
Rd ← dmem[Ra + SignExt(S)]
PC ← PC + 1
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.5.2. LDW: Indexed Load Word
Encoding (format 4):
0 0 1 0 1 0 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
LDW Rd,(Ra,S)
Constraints:
20 Copyright © 2015 Embecosm Limited
d≤7
-4 ≤ S ≤ 3
Outcome:
Rd ← dmem [Ra + SignExt(S)] | (dmem[Ra + SignExt(S) + 1] << 8)
PC ← PC + 1
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.5.3. LDB: Indexed Load Byte with Postincrement
Encoding (format 4):
0 0 1 0 0 0 1 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
LDB Rd,(Ra+,S)
Constraints:
d≤7
-4 ≤ S ≤ 3
Outcome:
Rd ← dmem[Ra + SignExt(S)]
Ra ← Ra + SignExt(S)
PC ← PC + 1
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.5.4. LDW: Indexed Load Word with Postincrement
Encoding (format 4):
0 0 1 0 1 0 1 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
LDW Rd,(Ra+,S)
Constraints:
d≤7
-4 ≤ S ≤ 3
Outcome:
Rd ← dmem[Ra + SignExt(S)] | (dmem[Ra + SignExt(S) + 1] << 8)
Ra ← Ra + SignExt(S)
PC ← PC + 1
Notes:
21 Copyright © 2015 Embecosm Limited
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.5.5. LDB: Indexed Load Byte with Predecrement
Encoding (format 4):
0 0 1 0 0 1 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
LDB Rd,(-Ra,S)
Constraints:
d≤7
-4 ≤ S ≤ 3
Outcome:
Ra ← Ra - SignExt(S)
Rd ← dmem[Ra]
PC ← PC + 1
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to
compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.5.6. LDW: Indexed Load Word with Predecrement
Encoding (format 4):
0 0 1 0 1 1 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
LDW Rd,(-Ra,S)
Constraints:
d≤7
-4 ≤ S ≤ 3
Outcome:
Ra ← Ra - SignExt(S)
Rd ← dmem[Ra] | (dmem[Ra + 1] << 8)
PC ← PC + 1
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to
compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
22 Copyright © 2015 Embecosm Limited
3.5.7. STB: Indexed Store Byte
Encoding (format 4):
0 0 1 1 0 0 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
STB (Rd,S),Ra
Constraints:
d≤7
-4 ≤ S ≤ 3
Outcome:
dmem[Rd + SignExt(S)] ← (Ra & 255)
PC ← PC + 1
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.5.8. STW: Indexed Store Word
Encoding (format 4):
0 0 1 1 1 0 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
STW (Rd,S),Ra
Constraints:
d≤7
-4 ≤ S ≤ 3
Outcome:
dmem[Rd + SignExt(S)] ← (Ra & 255)
dmem[Rd + SignExt(S) + 1] ← (Ra >> 8)
PC ← PC + 1
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.5.9. STB: Indexed Store Byte with Postincrement
Encoding (format 4):
0 0 1 1 0 0 1 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
STB (Rd+,S),Ra
Constraints:
23 Copyright © 2015 Embecosm Limited
d≤7
-4 ≤ S ≤ 3
Outcome:
dmem[Rd + SignExt(S)] ← (Ra & 255)
Rd ← Rd + SignExt(S)
PC ← PC + 1
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.5.10. STW: Indexed Store Word with Postincrement
Encoding (format 4):
0 0 1 1 1 0 1 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
STW (Rd+,S),Ra
Constraints:
d≤7
-4 ≤ S ≤ 3
Outcome:
dmem[Rd + SignExt(S)] ← (Ra & 255)
dmem[Rd + SignExt(S) + 1] ← (Ra >> 8)
Rd ← Rd + SignExt(S)
PC ← PC + 1
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.5.11. STB: Indexed Store Byte with Predecrement
Encoding (format 4):
0 0 1 1 0 1 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
STB (-Rd,S),Ra
Constraints:
d≤7
-4 ≤ S ≤ 3
Outcome:
Rd ← Rd - SignExt(S)
24 Copyright © 2015 Embecosm Limited
dmem[Rd] ← (Ra & 255)
PC ← PC + 1
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to
compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.5.12. STW: Indexed Store Word with Predecrement
Encoding (format 4):
0 0 1 1 1 1 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
Syntax:
STW (-Rd,S),Ra
Constraints:
d≤7
-4 ≤ S ≤ 3
Outcome:
Rd ← Rd - SignExt(S)
dmem[Rd] ← (Ra & 255)
dmem[Rd + 1] ← (Ra >> 8)
PC ← PC + 1
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to
compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.6. Detailed Descriptions of 16-bit Branch/Jump Instructions
Note
The only branch/jump comparisons provided are for "equal", "not equal", "less
than" and "greater than". Branch/jump comparisons for "less than or equal" and
"greater than or equal" can be provided by using "greater than" and "less than"
respectively in the opposite direction."
Purists will point out that this reduces the opportunity for branch prediction and
pipeline preservation. However the limited instruction space means not all opcodes
can be provided.
3.6.1. BRA: Relative Branch
Encoding (format 7):
0 1 0 0 0 0 0 s8 s7 s6 s5 s4 s3 s2 s1 s0
Syntax:
25 Copyright © 2015 Embecosm Limited
BRA S
Constraints:
-256 ≤ S ≤ 255
Outcome:
PC ← PC + SignExt(S)
Notes:
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.6.2. BAL: Relative Branch and Link
Encoding (format 6):
0 1 0 0 0 0 1 s5 s4 s3 s2 s1 s0 b2 b1 b0
Syntax:
BAL S,Rb
Constraints:
b≤7
-32 ≤ S ≤ 31
Outcome:
Rb ← PC + 1
PC ← PC + SignExt(S)
Notes:
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.6.3. BEQ: Relative Branch if Equal
Encoding (format 3):
0 1 0 0 0 1 0 s2 s1 s0 a2 a1 a0 b2 b1 b0
Syntax:
BEQ S,Ra,Rb
Constraints:
a≤7
b≤7
-4 ≤ S ≤ 3
Outcome:
PC ← (Ra = Rb) ? PC + SignExt(S) : PC + 1
26 Copyright © 2015 Embecosm Limited
Notes:
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.6.4. BNE: Relative Branch if Not Equal
Encoding (format 3):
0 1 0 0 0 1 1 s2 s1 s0 a2 a1 a0 b2 b1 b0
Syntax:
BNE S,Ra,Rb
Constraints:
a≤7
b≤7
-4 ≤ S ≤ 3
Outcome:
PC ← (Ra ≠ Rb) ? PC + SignExt(S) : PC + 1
Notes:
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.6.5. BLTS: Relative Branch if Signed Less Than
Encoding (format 3):
0 1 0 0 1 0 0 s2 s1 s0 a2 a1 a0 b2 b1 b0
Syntax:
BLTS S,Ra,Rb
Constraints:
a≤7
b≤7
-4 ≤ S ≤ 3
Outcome:
PC ← (Ra < Rb) ? PC + SignExt(S) : PC + 1
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each
register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
27 Copyright © 2015 Embecosm Limited
3.6.6. BLES: Relative Branch if Signed Less Than or Equal To
Encoding (format 3):
0 1 0 0 1 0 1 s2 s1 s0 a2 a1 a0 b2 b1 b0
Syntax:
BLES S,Ra,Rb
Constraints:
a≤7
b≤7
-4 ≤ S ≤ 3
Outcome:
PC ← (Ra ≤ Rb) ? PC + SignExt(S) : PC + 1
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each
register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.6.7. BLTU: Relative Branch if Unsigned Less Than
Encoding (format 3):
0 1 0 0 1 1 0 s2 s1 s0 a2 a1 a0 b2 b1 b0
Syntax:
BLTU S,Ra,Rb
Constraints:
a≤7
b≤7
-4 ≤ S ≤ 3
Outcome:
PC ← (Ra < Rb) ? PC + SignExt(S) : PC + 1
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.6.8. BLEU: Relative Branch if Unsigned Less Than or Equal To
Encoding (format 3):
0 1 0 0 1 1 1 s2 s1 s0 a2 a1 a0 b2 b1 b0
28 Copyright © 2015 Embecosm Limited
Syntax:
BLEU S,Ra,Rb
Constraints:
a≤7
b≤7
-4 ≤ S ≤ 3
Outcome:
PC ← (Ra ≤ Rb) ? PC + SignExt(S) : PC + 1
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.6.9. JMP: Absolute Jump
Encoding (format 1):
0 1 0 1 0 0 0 d2 d1 d0 0 0 0 0 0 0
Syntax:
JMP Rd
Constraints:
d≤7
Outcome:
PC ← Rd
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jumping to a non-existent location will trigger a bus error exception.
3.6.10. JAL: Absolute Jump and Link
Encoding (format 1):
0 1 0 1 0 0 1 d2 d1 d0 0 0 0 b2 b1 b0
Syntax:
JAL Rd,Rb
Constraints:
b≤7
d≤7
Outcome:
29 Copyright © 2015 Embecosm Limited
Rb ← PC + 1
PC ← Rd
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jumping to a non-existent location will trigger a bus error exception.
3.6.11. JEQ: Absolute Jump if Equal
Encoding (format 1):
0 1 0 1 0 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
JEQ Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
PC ← (Ra = Rb) ? Rd : PC + 1
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.6.12. JNE: Absolute Jump if Not Equal
Encoding (format 1):
0 1 0 1 0 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
JNE Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
PC ← (Ra ≠ Rb) ? Rd : PC + 1
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
30 Copyright © 2015 Embecosm Limited
3.6.13. JLTS: Absolute Jump if Signed Less Than
Encoding (format 1):
0 1 0 1 1 0 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
JLTS Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
PC ← (Ra < Rb) ? Rd : PC + 1
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each
register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.6.14. JLES: Absolute Jump if Signed Less Than or Equal To
Encoding (format 1):
0 1 0 1 1 0 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
JLES Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
PC ← (Ra ≤ Rb) ? Rd : PC + 1
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each
register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.6.15. JLTU: Absolute Jump if Unsigned Less Than
Encoding (format 1):
31 Copyright © 2015 Embecosm Limited
0 1 0 1 1 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
JLTU Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
PC ← (Ra < Rb) ? Rd : PC + 1
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.6.16. JLEU: Absolute Jump if Unsigned Less Than or Equal To
Encoding (format 1):
0 1 0 1 1 1 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
Syntax:
JLEU Rd,Ra,Rb
Constraints:
a≤7
b≤7
d≤7
Outcome:
PC ← (Ra ≤ Rb) ? Rd : PC + 1
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.7. Detailed Descriptions of 16-bit Miscellaneous Instructions
3.7.1. RTE: Return from Exception
Encoding (format 1):
0 1 1 0 0 0 0 d2 d1 d0 0 0 0 0 0 0
Syntax:
32 Copyright © 2015 Embecosm Limited
RTE Rd
Constraints:
d≤7
Outcome:
PC ← Rd
Notes:
This opcode is not fully defined, pending agreement on the exception mechanism for AAP.
3.8. Detailed Descriptions of 32-bit ALU Instructions
At this time, this section is incomplete.
3.8.1. NOP: No Operation
Encoding (format 14, first word at lower address):
1 0 0 0 0 0 0 d 2 d 1 d 0 i5 i4 i3 i2 i1 i0
0 0 0 0 0 0 0 d5 d4 d3 i11 i10 i9 i8 i7 i6
Syntax:
NOP Rd,I
Constraints:
d ≤ 63
I ≤ 4095
Outcome:
PC ← PC + 1
Notes:
This opcode may trigger side-effects in implementations, depending on the value of I,
particularly when simulating (see Section 2.3).
There are no conventions for any values of d or I for the 32-bit version of NOP.
3.8.2. ADD: Unsigned Add
Encoding (format 8, first word at lower address):
1 0 0 0 0 0 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
ADD Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
33 Copyright © 2015 Embecosm Limited
Outcome:
Rd ← R a + R b
carry ← ( ( Ra + Rb ) ≥ 216 ) ? 1 : 0
PC ← PC + 2
3.8.3. SUB: Unsigned Subtract
Encoding (format 8, first word at lower address):
1 0 0 0 0 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
SUB Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
Rd ← Ra - Rb
carry ← ( Rb > Ra ) ? 1 : 0
PC ← PC + 2
3.8.4. AND: Bitwise AND
Encoding (format 8, first word at lower address):
1 0 0 0 0 1 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
AND Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
Rd ← Ra & Rb
PC ← PC + 2
3.8.5. OR: Bitwise OR
Encoding (format 8, first word at lower address):
1 0 0 0 1 0 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
34 Copyright © 2015 Embecosm Limited
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
OR Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
Rd ← R a | R b
PC ← PC + 2
3.8.6. XOR: Bitwise Exclusive OR
Encoding (format 8, first word at lower address):
1 0 0 0 1 0 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
XOR Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
Rd ← R a ^ R b
PC ← PC + 2
3.8.7. ASR: Arithmetic Shift Right
Encoding (format 8, first word at lower address):
1 0 0 0 1 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
ASR Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
35 Copyright © 2015 Embecosm Limited
Rd ← ( Ra | ( carry << 16 ) ) >> Rb )
carry ← 0
PC ← PC + 2
Notes:
If Rb ≥ 17 the result in Rd will be zero.
The carry flag is always cleared, even if a shift of zero is specified.
3.8.8. LSL: Logical Shift Left
Encoding (format 8, first word at lower address):
1 0 0 0 1 1 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
LSL Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
Rd ← Ra << Rb
PC ← PC + 2
Notes:
If Rb ≥ 16 the result in Rd will be zero.
3.8.9. LSR: Logical Shift Right
Encoding (format 8, first word at lower address):
1 0 0 1 0 0 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
LSR Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
Rd ← Ra >> Rb
PC ← PC + 2
36 Copyright © 2015 Embecosm Limited
Notes:
If Rb ≥ 16 the result in Rd will be zero.
3.8.10. MOV: Move Register to Register
Encoding (format 8, first word at lower address):
1 0 0 1 0 0 1 d2 d1 d0 a2 a1 a0 0 0 0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 0 0 0
Syntax:
MOV Rd,Ra
Constraints:
a ≤ 63
d ≤ 63
Outcome:
Rd ← R a
PC ← PC + 2
3.8.11. ADDI: Unsigned Add Immediate
Encoding (format 11, first word at lower address):
1 0 0 1 0 1 0 d2 d1 d0 a2 a1 a0 i2 i1 i0
0 0 0 i9 i8 i7 i6 d5 d4 d3 a5 a4 a3 i5 i4 i3
Syntax:
ADDI Rd,Ra,I
Constraints:
a ≤ 63
d ≤ 63
I ≤ 63
Outcome:
Rd ← R a + I
carry ← ( ( Ra + I ) ≥ 216 ) ? 1 : 0
PC ← PC + 2
Notes:
Adding constant zero can be used to clear the carry flag.
3.8.12. SUBI: Unsigned Subtract Immediate
Encoding (format 11, first word at lower address):
1 0 0 1 0 1 1 d2 d1 d0 a2 a1 a0 i2 i1 i0
0 0 0 i9 i8 i7 i6 d5 d4 d3 a5 a4 a3 i5 i4 i3
37 Copyright © 2015 Embecosm Limited
Syntax:
SUBI Rd,Ra,I
Constraints:
a ≤ 63
d ≤ 63
I ≤ 63
Outcome:
Rd ← R a - I
carry ← ( I > Ra ) ? 1 : 0
PC ← PC + 2
3.8.13. ASRI: Arithmetic Shift Right Immediate
Encoding (format 9, first word at lower address):
1 0 0 1 1 0 0 d2 d1 d0 a2 a1 a0 i2 i1 i0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 i5 i4 i3
Syntax:
ASRI Rd,Ra,I
Constraints:
a ≤ 63
d ≤ 63
1 ≤ I ≤ 64
Outcome:
Rd ← ( Ra | ( carry << 16 ) ) >> I )
carry ← 0
PC ← PC + 2
Notes:
If I ≥ 17 the result in Rd will be zero.
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as
0000002. The rationale is that shifting by zero is pointless. It is not needed to clear the
carry flag, since there are other ways of clearing the it (for example adding constant zero).
3.8.14. LSLI: Logical Shift Left Immediate
Encoding (format 9, first word at lower address):
1 0 0 1 1 0 1 d2 d1 d0 a2 a1 a0 i2 i1 i0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 i5 i4 i3
Syntax:
LSLI Rd,Ra,I
38 Copyright © 2015 Embecosm Limited
Constraints:
a ≤ 63
d ≤ 63
1 ≤ I ≤ 64
Outcome:
Rd ← Ra << I
PC ← PC + 2
Notes:
If I ≥ 16 the result in Rd will be zero.
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as
0000002. The rationale is that shifting by zero is pointless. It is not needed to clear the
carry flag, since there are other ways of clearing the it (for example adding constant zero).
3.8.15. LSRI: Logical Shift Right Immediate
Encoding (format 9, first word at lower address):
1 0 0 1 1 1 0 d2 d1 d0 a2 a1 a0 i2 i1 i0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 i5 i4 i3
Syntax:
LSRI Rd,Ra,I
Constraints:
a ≤ 63
d ≤ 63
1 ≤ I ≤ 64
Outcome:
Rd ← Ra >> I
PC ← PC + 2
Notes:
If I ≥ 16 the result in Rd will be zero.
The shift is encoded with a value 1 less than specified (i.e. a shift of 1 is encoded as
0000002. The rationale is that shifting by zero is pointless. It is not needed to clear the
carry flag, since there are other ways of clearing the it (for example adding constant zero).
3.8.16. MOVI: Move Immediate to Register
Encoding (format 15, first word at lower address):
1 0 0 1 1 1 1 d 2 d 1 d 0 i5 i4 i3 i2 i1 i0
0 0 0 i15 i14 i13 i12 d5 d4 d3 i11 i10 i9 i8 i7 i6
Syntax:
MOVI Rd,I
39 Copyright © 2015 Embecosm Limited
Constraints:
d ≤ 63
I ≤ 65535
Outcome:
Rd ← I
PC ← PC + 2
3.8.17. ADDC: Unsigned Add with Carry
Encoding (format 8, first word at lower address):
1 0 0 0 0 0 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 1 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
ADDC Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
Rd ← Ra + Rb + carry
carry ← ( ( Ra + Rb + carry) ≥ 216 ) ? 1 : 0
PC ← PC + 2
3.8.18. SUBC: Unsigned Subtract with Carry
Encoding (format 8, first word at lower address):
1 0 0 0 0 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 1 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
SUBC Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
Rd ← Ra - Rb - carry
carry ← ((Rb + carry) > Ra) ? 1 : 0
PC ← PC + 2
40 Copyright © 2015 Embecosm Limited
3.8.19. ANDI: Bitwise AND Immediate
Encoding (format 10, first word at lower address):
1 0 0 0 0 1 1 d2 d1 d0 a2 a1 a0 i2 i1 i0
0 0 0 i8 i7 i6 1 d5 d4 d3 a5 a4 a3 i5 i4 i3
Syntax:
ANDI Rd,Ra,I
Constraints:
a ≤ 63
d ≤ 63
I ≤ 511
Outcome:
Rd ← R a & I
PC ← PC + 2
3.8.20. ORI: Bitwise OR immediate
Encoding (format 10, first word at lower address):
1 0 0 0 1 0 0 d2 d1 d0 a2 a1 a0 i2 i1 i0
0 0 0 i8 i7 i6 1 d5 d4 d3 a5 a4 a3 i5 i4 i3
Syntax:
ORI Rd,Ra,I
Constraints:
a ≤ 63
d ≤ 63
I ≤ 511
Outcome:
Rd ← R a | I
PC ← PC + 2
3.8.21. XORI: Bitwise Exclusive OR Immediate
Encoding (format 10, first word at lower address):
1 0 0 0 1 0 1 d2 d1 d0 a2 a1 a0 i2 i1 i0
0 0 0 i8 i7 i6 1 d5 d4 d3 a5 a4 a3 i5 i4 i3
Syntax:
XORI Rd,Ra,I
Constraints:
41 Copyright © 2015 Embecosm Limited
a ≤ 63
d ≤ 63
I ≤ 511
Outcome:
Rd ← R a ^ I
PC ← PC + 2
3.9. Detailed Descriptions of 32-bit Load/Store Instructions
3.9.1. LDB: Indexed Load Byte
Encoding (format 13, first word at lower address):
1 0 1 0 0 0 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
LDB Rd,(Ra,S)
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
Rd ← dmem[Ra + SignExt(S)]
PC ← PC + 2
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.9.2. LDW: Indexed Load Word
Encoding (format 13, first word at lower address):
1 0 1 0 1 0 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
LDW Rd,(Ra,S)
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
Rd ← dmem [Ra + SignExt(S)] | (dmem[Ra + SignExt(S) + 1] << 8)
PC ← PC + 2
42 Copyright © 2015 Embecosm Limited
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.9.3. LDB: Indexed Load Byte with Postincrement
Encoding (format 13, first word at lower address):
1 0 1 0 0 0 1 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
LDB Rd,(Ra+,S)
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
Rd ← dmem[Ra + SignExt(S)]
Ra ← Ra + SignExt(S)
PC ← PC + 2
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.9.4. LDW: Indexed Load Word with Postincrement
Encoding (format 13, first word at lower address):
1 0 1 0 1 0 1 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
LDW Rd,(Ra+,S)
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
Rd ← dmem [Ra + SignExt(S)] | (dmem[Ra + SignExt(S) + 1] << 8)
Ra ← Ra + SignExt(S)
PC ← PC + 2
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
43 Copyright © 2015 Embecosm Limited
3.9.5. LDB: Indexed Load Byte with Predecrement
Encoding (format 13, first word at lower address):
1 0 1 0 0 1 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
LDB Rd,(-Ra,S)
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
Ra ← Ra - SignExt(S)
Rd ← dmem[Ra]
PC ← PC + 2
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.9.6. LDW: Indexed Load Word with Predecrement
Encoding (format 13, first word at lower address):
1 0 1 0 1 1 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
LDW Rd,(-Ra,S)
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
Ra ← Ra - SignExt(S)
Rd ← dmem [Ra] | (dmem[Ra + 1] << 8)
PC ← PC + 2
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.9.7. STB: Indexed Store Byte
Encoding (format 13, first word at lower address):
1 0 1 1 0 0 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
44 Copyright © 2015 Embecosm Limited
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
STB (Rd,S),Ra
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
dmem[Rd + SignExt(S)] ← (Ra & 255)
PC ← PC + 2
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.9.8. STW: Indexed Store Word
Encoding (format 13, first word at lower address):
0 0 1 1 1 0 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
STW (Rd,S),Ra
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
dmem[Rd + SignExt(S)] ← (Ra & 255)
dmem[Rd + SignExt(S) + 1] ← (Ra >> 8)
PC ← PC + 2
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.9.9. STB: Indexed Store Byte with Postincrement
Encoding (format 13, first word at lower address):
1 0 1 1 0 0 1 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
STB (Rd+,S),Ra
Constraints:
45 Copyright © 2015 Embecosm Limited
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
dmem[Rd + SignExt(S)] ← (Ra & 255)
Rd ← Rd + SignExt(S)
PC ← PC + 2
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.9.10. STW: Indexed Store Word with Postincrement
Encoding (format 13, first word at lower address):
1 0 1 1 1 0 1 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
STW (Rd+,S),Ra
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
dmem[Rd + SignExt(S)] ← (Ra & 255)
dmem[Rd + SignExt(S) + 1] ← (Ra >> 8)
Rd ← Rd + SignExt(S)
PC ← PC + 2
Notes:
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.9.11. STB: Indexed Store Byte with Predecrement
Encoding (format 13, first word at lower address):
1 0 1 1 0 1 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
STB (-Rd,S),Ra
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
46 Copyright © 2015 Embecosm Limited
Outcome:
Rd ← Rd - SignExt(S)
dmem[Rd] ← (Ra & 255)
PC ← PC + 2
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to
compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.9.12. STW: Indexed Store Word with Predecrement
Encoding (format 13, first word at lower address):
1 0 1 1 1 1 0 d2 d1 d0 a2 a1 a0 s2 s1 s0
0 0 0 s9 s8 s7 s6 d5 d4 d3 a5 a4 a3 s5 s4 s3
Syntax:
STW (-Rd,S),Ra
Constraints:
d ≤ 63
-512 ≤ S ≤ 511
Outcome:
Rd ← Rd - SignExt(S)
dmem[Rd] ← (Ra & 255)
dmem[Rd + 1] ← (Ra >> 8)
PC ← PC + 2
Notes:
For the avoidance of doubt, the decrement of Ra is carried out before Ra is used to
compute the address for loading.
This opcode accesses data memory, and the computed address is therefore a byte
address. Accessing a non-existent memory location will trigger a bus error exception.
3.10. Detailed Descriptions of 32-bit Branch/Jump Instructions
Note
As with the 16-bit instructions, only a limited range of comparisons is provided.
See Section 3.6 for an explanation.
3.10.1. BRA: Relative Branch
Encoding (format 17, first word at lower address):
1 1 0 0 0 0 0 s8 s7 s6 s5 s4 s3 s2 s1 s0
0 0 0 s21 s20 s19 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9
47 Copyright © 2015 Embecosm Limited
Syntax:
BRA S
Constraints:
-2,097,152 ≤ S ≤ 2,097,151
Outcome:
PC ← PC + SignExt(S)
Notes:
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.10.2. BAL: Relative Branch and Link
Encoding (format 16, first word at lower address):
1 1 0 0 0 0 1 s5 s4 s3 s2 s1 s0 b2 b1 b0
0 0 0 s18 s17 s16 s15 s14 s13 s12 s11 s10 s9 b5 b4 b3
Syntax:
BAL S,Rb
Constraints:
b ≤ 63
-262,144 ≤ S ≤ 262,141
Outcome:
Rb ← PC + 2
PC ← PC + SignExt(S)
Notes:
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.10.3. BEQ: Relative Branch if Equal
Encoding (format 12, first word at lower address):
1 1 0 0 0 1 0 s2 s1 s0 a2 a1 a0 b2 b1 b0
0 0 0 s9 s8 s7 s6 s5 s4 s3 a5 a4 a3 b5 b4 b3
Syntax:
BEQ S,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
48 Copyright © 2015 Embecosm Limited
-512 ≤ S ≤ 511
Outcome:
PC ← (Ra = Rb) ? PC + SignExt(S) : PC + 2
Notes:
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.10.4. BNE: Relative Branch if Not Equal
Encoding (format 12, first word at lower address):
1 1 0 0 0 1 1 s2 s1 s0 a2 a1 a0 b2 b1 b0
0 0 0 s9 s8 s7 s6 s5 s4 s3 a5 a4 a3 b5 b4 b3
Syntax:
BNE S,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
-512 ≤ S ≤ 511
Outcome:
PC ← (Ra ≠ Rb) ? PC + SignExt(S) : PC + 2
Notes:
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.10.5. BLTS: Relative Branch if Signed Less Than
Encoding (format 12, first word at lower address):
1 1 0 0 1 0 0 s2 s1 s0 a2 a1 a0 b2 b1 b0
0 0 0 s9 s8 s7 s6 s5 s4 s3 a5 a4 a3 b5 b4 b3
Syntax:
BLTS S,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
-512 ≤ S ≤ 511
Outcome:
PC ← (Ra < Rb) ? PC + SignExt(S) : PC + 2
49 Copyright © 2015 Embecosm Limited
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each
register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.10.6. BLES: Relative Branch if Signed Less Than or Equal To
Encoding (format 12, first word at lower address):
1 1 0 0 1 0 1 s2 s1 s0 a2 a1 a0 b2 b1 b0
0 0 0 s9 s8 s7 s6 s5 s4 s3 a5 a4 a3 b5 b4 b3
Syntax:
BLES S,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
-512 ≤ S ≤ 511
Outcome:
PC ← (Ra ≤ Rb) ? PC + SignExt(S) : PC + 2
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each
register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.10.7. BLTU: Relative Branch if Unsigned Less Than
Encoding (format 12, first word at lower address):
1 1 0 0 1 1 0 s2 s1 s0 a2 a1 a0 b2 b1 b0
0 0 0 s9 s8 s7 s6 s5 s4 s3 a5 a4 a3 b5 b4 b3
Syntax:
BLTU S,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
-512 ≤ S ≤ 511
Outcome:
PC ← (Ra < Rb) ? PC + SignExt(S) : PC + 2
50 Copyright © 2015 Embecosm Limited
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.10.8. BLEU: Relative Branch if Unsigned Less Than or Equal To
Encoding (format 12, first word at lower address):
1 1 0 0 1 1 1 s2 s1 s0 a2 a1 a0 b2 b1 b0
0 0 0 s9 s8 s7 s6 s5 s4 s3 a5 a4 a3 b5 b4 b3
Syntax:
BLEU S,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
-512 ≤ S ≤ 511
Outcome:
PC ← (Ra ≤ Rb) ? PC + SignExt(S) : PC + 2
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the offset is the number of
words by which to adjust the PC.
Branching to a non-existent location will trigger a bus error exception.
3.10.9. JMP: Absolute Jump
Encoding (format 8, first word at lower address):
1 1 0 1 0 0 0 d2 d1 d0 0 0 0 0 0 0
0 0 0 1 0 0 0 d5 d4 d3 0 0 0 0 0 0
Syntax:
JMP Rd
Constraints:
d ≤ 63
Outcome:
PC ← Rd
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
51 Copyright © 2015 Embecosm Limited
Jumping to a non-existent location will trigger a bus error exception.
3.10.10. JAL: Absolute Jump and Link
Encoding (format 8, first word at lower address):
1 1 0 1 0 0 1 d2 d1 d0 0 0 0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 0 0 0 b5 b4 b3
Syntax:
JAL Rd,Rb
Constraints:
b ≤ 63
d ≤ 63
Outcome:
Rb ← PC + 2
PC ← Rd
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jumping to a non-existent location will trigger a bus error exception.
3.10.11. JEQ: Absolute Jump if Equal
Encoding (format 8, first word at lower address):
1 1 0 1 0 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JEQ Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
PC ← (Ra = Rb) ? Rd : PC + 2
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.12. JNE: Absolute Jump if Not Equal
Encoding (format 8, first word at lower address):
52 Copyright © 2015 Embecosm Limited
1 1 0 1 0 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JNE Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
PC ← (Ra ≠ Rb) ? Rd : PC + 2
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.13. JLTS: Absolute Jump if Signed Less Than
Encoding (format 8, first word at lower address):
1 1 0 1 1 0 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JLTS Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
PC ← (Ra < Rb) ? Rd : PC + 2
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each
register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.14. JLES: Absolute Jump if Signed Less Than or Equal To
Encoding (format 8, first word at lower address):
1 1 0 1 1 0 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
53 Copyright © 2015 Embecosm Limited
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JLES Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
PC ← (Ra ≤ Rb) ? Rd : PC + 2
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each
register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.15. JLTU: Absolute Jump if Unsigned Less Than
Encoding (format 8, first word at lower address):
1 1 0 1 1 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JLTU Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
PC ← (Ra < Rb) ? Rd : PC + 2
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.16. JLEU: Absolute Jump if Unsigned Less Than or Equal To
Encoding (format 8, first word at lower address):
1 1 0 1 1 1 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
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0 0 0 0 0 0 0 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JLEU Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 63
Outcome:
PC ← (Ra ≤ Rb) ? Rd : PC + 2
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.17. JMPL: Absolute Jump Long
Encoding (format 8, first word at lower address):
1 1 0 1 0 0 0 d2 d1 d0 0 0 0 0 0 0
0 0 0 0 0 0 1 d5 d4 d3 0 0 0 0 0 0
Syntax:
JMPL Rd
Constraints:
d ≤ 62
(d % 2) = 2
Outcome:
PC ← (Rd+1 << 16) | Rd
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jumping to a non-existent location will trigger a bus error exception.
3.10.18. JALL: Absolute Jump Long and Link
Encoding (format 8, first word at lower address):
1 1 0 1 0 0 1 d2 d1 d0 0 0 0 b2 b1 b0
0 0 0 0 0 0 1 d5 d4 d3 0 0 0 b5 b4 b3
Syntax:
55 Copyright © 2015 Embecosm Limited
JALL Rd,Rb
Constraints:
b ≤ 63
d ≤ 62
(d % 2) = 2
Outcome:
Rb ← PC + 2
PC ← (Rd+1 << 16) | Rd
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jumping to a non-existent location will trigger a bus error exception.
3.10.19. JEQL: Absolute Jump Long if Equal
Encoding (format 8, first word at lower address):
1 1 0 1 0 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 1 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JEQL Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 62
(d % 2) = 2
Outcome:
PC ← (Ra = Rb) ? ((Rd+1 << 16) | Rd) : PC + 2
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.20. JNEL: Absolute Jump Long if Not Equal
Encoding (format 8, first word at lower address):
1 1 0 1 0 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 1 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JNEL Rd,Ra,Rb
56 Copyright © 2015 Embecosm Limited
Constraints:
a ≤ 63
b ≤ 63
d ≤ 62
(d % 2) = 2
Outcome:
PC ← (Ra ≠ Rb) ? ((Rd+1 << 16) | Rd) : PC + 2
Notes:
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.21. JLTSL: Absolute Jump Long if Signed Less Than
Encoding (format 8, first word at lower address):
1 1 0 1 1 0 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 1 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JLTSL Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 62
(d % 2) = 2
Outcome:
PC ← (Ra < Rb) ? ((Rd+1 << 16) | Rd) : PC + 2
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each
register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.22. JLESL: Absolute Jump Long if Signed Less Than or Equal To
Encoding (format 8, first word at lower address):
1 1 0 1 1 0 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 1 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
57 Copyright © 2015 Embecosm Limited
JLESL Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 62
(d % 2) = 2
Outcome:
PC ← (Ra ≤ Rb) ? ((Rd+1 << 16) | Rd) : PC + 2
Notes:
The comparison between Ra and Rb is a signed comparison, where the contents of each
register is treated as a 2's-complement signed number.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.23. JLTUL: Absolute Jump Long if Unsigned Less Than
Encoding (format 8, first word at lower address):
1 1 0 1 1 1 0 d2 d1 d0 a2 a1 a0 b2 b1 b0
0 0 0 0 0 0 1 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JLTUL Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 62
(d % 2) = 2
Outcome:
PC ← (Ra < Rb) ? ((Rd+1 << 16) | Rd) : PC + 2
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.10.24. JLEUL: Absolute Jump Long if Unsigned Less Than or Equal To
Encoding (format 8, first word at lower address):
1 1 0 1 1 1 1 d2 d1 d0 a2 a1 a0 b2 b1 b0
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0 0 0 0 0 0 1 d5 d4 d3 a5 a4 a3 b5 b4 b3
Syntax:
JLEUL Rd,Ra,Rb
Constraints:
a ≤ 63
b ≤ 63
d ≤ 62
(d % 2) = 2
Outcome:
PC ← (Ra ≤ Rb) ? ((Rd+1 << 16) | Rd) : PC + 2
Notes:
The comparison between Ra and Rb is an unsigned comparison.
Remember that the program counter is a word address, so the value in Rd should be
a word address.
Jump to a non-existent location will trigger a bus error exception.
3.11. Detailed Descriptions of 32-bit Miscellaneous Instructions
There are currently no 32-bit instructions defined in this class.
59 Copyright © 2015 Embecosm Limited
Chapter 4. ABI
4.1. Defined Registers
Because of the variability in the architecture it is difficult to be too rigid on the ABI. In any
case part of the purpose of this architecture to allow exploration of different ABI's. Within this
section, the identifier Rmax is used to indicate the highest numbered register in the architecture.
The meanings of the following registers are defined.
• R0: Link Register
• R1: Stack Pointer
Note in particular no frame pointer is defined. It is up to the implementer to decide policy with
regard to use of a frame pointer.
4.2. Calling Convention
Again this is flexible, particularly where there can be very few registers. These are the general
guidelines.
• All byte arguments are promoted to 16-bits.
• Arguments are passed in R2–R7 (or R2–Rmax if there are fewer than 8 registers).
• Results are returned on the same registers used to pass arguments.
• Varargs are always passed on the stack.
• A good guideline is that approximately one third of unallocated registers should be caller
saved, although that can increase to one half where there are plenty of registers. The
following registers (if present) are caller saved: R10, R13, R16, R19, R22, R25, R28, R31, R33,
R35, R37, R39, R41, R43, R45, R47, R49, R51, R53, R55, R57, R59, R61 and R63.
60 Copyright © 2015 Embecosm Limited