1 2 3 4 5 6
P1.9VA COU10AB
U10AB
10uF, 10V, X5R, 20%
2
PIU10A02 1
VA GND PIU10A01
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
22uF, 6.3V, X5R, 20%
5 6
PIC10A01 PIC1 A01 PIC12A01 PIC13A01 PIC14A01 PIC15A01 PIC16A01 PIC17A01 PIC18A01 PIC19A01 PIC20A01 PIC21A02 PIU10A05 VA GND PIU10A06
8
PIU10A08 VA
9
COC10A
C10A COC11A
C11A COC12A
C12A COC13A
C13A COC14A
C14A COC15A
C15A COC16A
C16A COC17A
C17A COC18A
C18A COC19A
C19A COC20A
C20A COC21A
C21A GND PIU10A09
13 12
PIC10A02 PIC1 A02 PIC12A02 PIC13A02 PIC14A02 PIC15A02 PIC16A02 PIC17A02 PIC18A02 PIC19A02 PIC20A02 PIC21A01 PIU10A013 VA GND PIU10A012
16 21
PIU10A016 VA GND PIU10A021
17 24
PIU10A017 VA GND PIU10A024
20
PIU10A020 VA 27
A GND PIU10A027 A
25
PIU10A025 VA
GND 28
PIU10A028 VA
33
PIU10A033 VA
128
PIU10A0128 129
VA DAP PIU10A0129
P1.9VD
10uF, 10V, X5R, 20%
Note for FPGA design: LVDS with 100-ohm terms required!
40 42 GND
PIU10A040 VDR DRGND PIU10A042
22uF, 6.3V, X5R, 20%
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
51
PIU10A051 VDR
53
COU10AA PIC2 A01 PIC23A01 PIC24A01 PIC25A01 PIC26A01 PIC27A01 PIC28A01 PIC29A01 PIC30A01 PIC31A02 DRGND PIU10A053
U10AA 62
PIU10A062 VDR
64
NLVIN0A0P COC22A
C22A COC23A
C23A COC24A
C24A COC25A
C25A COC26A
C26A COC27A
C27A COC28A
C28A COC29A
C29A COC30A
C30A COC31A
C31A DRGND PIU10A064
VIN_A_P 11 103 F_LVDS1_P 73 74
NLVIN0A0N PIU10A011 VINI+ DI0+ PIU10A0103 PIC2 A02 PIC23A02 PIC24A02 PIC25A02 PIC26A02 PIC27A02 PIC28A02 PIC29A02 PIC30A02 PIC31A01 PIU10A073 VDR DRGND PIU10A074
VIN_A_N 10 102 F_LVDS1_N 88 87
PIU10A010 VINI- DI0- PIU10A0102 PIU10A088 VDR DRGND PIU10A087
validate that FPGA can take 500MHz GCLK in to SERDES 101 F_LVDS5_P 99 97
Note: LVDSC swap for DVT
NLVIN0B0P DI1+ PIU10A0101 PIU10A099 VDR DRGND PIU10A097
VIN_B_P 22 100 F_LVDS5_N 110 108
NLVIN0B0N
PIU10A022 VINQ+ DI1- PIU10A0100 PIU10A0110 VDR DRGND PIU10A0108
VIN_B_N 23 96 F_LVDS11_P GND 121 119
PIU10A023 VINQ- DI2+ PIU10A096 PIU10A0121 VDR DRGND PIU10A0119
95
PIU10A095 F_LVDS11_N
DI2-
coordinate to PLL powerdown NLF0LVDX12
F_LVDX12 26
PIU10A026 94 F_LVDSC_N 32 63
NLF0LVDX6 PD DI3+ PIU10A094 PIU10A032 REXT NC PIU10A063
F_LVDX6 29
PIU10A029 93 F_LVDSC_P 98
PDQ DI3- PIU10A093 NC PIU10A098
92 F_LVDS15_P 34 109
DI4+ PIU10A092 PIU10A034 TDIODE_P NC PIU10A0109
14
PIU10A014 FSR/ALT_ECE/DCLK_RST-
91 F_LVDS15_N 35 120
NLADC0ECE DI4- PIU10A091 PIU10A035 TDIODE_N NC PIU10A0120
ADC_ECE 41
PIU10A041 ECE
90 F_LVDS0_P
DI5+ PIU10A090 GND
89 F_LVDS0_N ADC08D1020CIYB/NOPB
PIR10A01 DI5- PIU10A089 PIR1 A01
SCLK NLF0LVDX14
F_LVDX14 3
PIU10A03 OUTV/SCLK
86 F_LVDS4_P COJP1
JP1
COR10A
R10A DI6+ PIU10A086
NLF0DX5 COR11A
R11A
85 F_LVDS4_N F_DX5
DI6- PIU10A085 PIJP10A1 A1 B1 PIJP10B1
PIR21A01COR21A NLADC0CLKIN0P F_DX0
100, 1%
1k, 1% ADC_CLKIN_P 18
PIU10A018 CLK+
84 F_LVDS2_P NLF0DX0 NLF0DX4
F_DX4 3.3k, 0.1%, 1/16W, 25ppm/C
DI7+ PIU10A084 PIJP10A2 A2 B2 PIJP10B2
B
P3.3V_D PIR10A 2 R21A NLADC0CLKIN0N
ADC_CLKIN_N 19
PIU10A019 CLK-
83
DI7- PIU10A083
F_LVDS2_N
F_DX3
NLF0DX3
F_DX2 PIJP10A3 A3 B3 PIJP10B3
NLDDC0SCL
DDC_SCL PIR1 A02 B
P1.9VD NLF0DX2 PIJP10A4 A4
NLF0LVDS140P
F_LVDS14_P
B4 PIJP10B4
PIR12A01 PIR21A02
SDATA NLF0LVDX15
F_LVDX15 4
PIU10A04 OUTEDGE/DDR/SDATA
125
DID0+ PIU10A0125
F_DX11
NLF0DX11 PIJP10A5 A5 B5 PIJP10B5
NLF0LVDS140N
F_LVDS14_N
COR12A
R12A PIR13A01 GND 124
DDC_SDA
NLDDC0SDA GND
47k, 1% COR13A
R13A NLF0LVDX13 DID0- PIU10A0124 PIJP10GND1 GND1 GND5 PIJP10GND5 NLF0DX8
F_LVDX13 15
PIU10A015 123 F_DX8 GND
DCLK_RST/DCLK_RST+ DID1+ PIU10A0123 PIJP10A6 A6 B6 PIJP10B6
PIR12A02 1k, 1% 122
DID1- PIU10A0122
F_LVDS11_P
NLF0LVDS110P
PIJP10A7 A7 B7 PIJP10B7
PIR13A02 NLADC0DRST0SEL
ADC_DRST_SEL 52
PIU10A052 DRST_SEL
118
DID2+ PIU10A0118
F_LVDS11_N
NLF0LVDS110N
F_DX1 PIJP10A8 A8 B8 PIJP10B8
NLF0LVDS130P
F_LVDS13_P
F_DX18 117 NLF0DX1 NLF0LVDS130N
F_LVDS13_N
COR14A
R14A NLADC0CAL DID2- PIU10A0117 F_LVDSC_N
NLF0LVDSC0N PIJP10A9 A9 B9 PIJP10B9 NLF0DX16
ADC_CAL 30 116 F_DX16
PIR14A01 PIR14A02 PIU10A030 CAL DID3+ PIU10A0116 PIJP10A10 A10 B10 PIJP10B10
PIQ10A3 NLF0LVDX7 F_LVDSC_P
NLF0LVDSC0P NLF0LVDS120P
1k, 1% SCS F_LVDX7 127 115 F_LVDS12_P
CALDLY/DES/SCS DID3- PIU10A0115 PIJP10A11 A11 B11 PIJP10B11
3
PIU10A0127
COQ10A
Q10A GND 114 NLF0LVDS120N
F_LVDS12_N P1.9VA
BSS138 NLADC0CALRUN DID4+ PIU10A0114 NLF0DX17
F_DX17 PIJP10A12 A12 B12 PIJP10B12
1 ADC_CALRUN 126 113
PIQ10A01 PIU10A0126 CALRUN DID4- PIU10A0113 PIJP10A13 A13 B13 PIJP10B13
112 NLF0LVDS100N
F_LVDS10_N COU11A
U11A
DID5+ PIU10A0112 F_LVDSB_P PIJP10A14 A14 B14 PIJP10B14
PIQ10A 2 F_LVDS6_P 79
PIU10A079 OR+/DCLK2+
111
DID5- PIU10A0111
swap NLF0LVDSB0P PIJP10A15 A15 B15 PIJP10B15
NLF0LVDS100P
F_LVDS10_P swap
COR15A
P2.3V 1
PIU11A01 EN
8
GND PIU11A08
2
R15A
ballast to prevent spiking
F_LVDSB_N
F_LVDS6_N 80
PIU10A080 107 NLF0LVDSB0N 2 7
OR-/DCLK2- DID6+ PIU10A0107 PIJP10GND2 GND2 GND6 PIJP10GND6 NLF0DX18
PIR15A01 PIR15A02 PIU11A02 IN GND PIU11A07
106 F_DX18 88.7, 0.1% 3 6
DID6- PIU10A0106 PIJP10A16 A16 B16 PIJP10B16 PIU11A03 OUT GND PIU11A06
Note for FPGA design: LVDS with 100-ohm terms required!
F_LVDS15_P
F_LVDS_CK0_P 82
PIU10A082 105
PIU10A0105
NLF0LVDS150P PIJP10A17 A17 4 5
DCLK+ DID7+ F_LVDS15_N
NLF0LVDS150N B17 PIJP10B17 NLF0LVDS0CK00N
PIU11A04 ADJ GND PIU11A05
GND F_LVDS_CK0_N 81 104 F_LVDS_CK0_N
PIU10A081 DCLK- DID7- PIU10A0104 PIJP10A18 A18 B18 PIJP10B18
10uF, 10V, X5R, 20%
10uF, 10V, X5R, 20%
F_LVDS0_P PIJP10A19 A19 B19 PIJP10B19
NLF0LVDS0CK00P
F_LVDS_CK0_P swap PIR16A01 PIR17A01 MIC37122YM
NLADC0VCMO
ADC_VCMO 7 58 F_LVDS14_P NLF0LVDS00P COR16A
R16A COR17A
R17A
PIU10A07 VCMO DQ0+ PIU10A058 F_LVDS0_N
NLF0LVDS00N PIJP10A20 A20 B20 PIJP10B20 NLF0LVDS90P 100, 1% 100, 0.5% PIC32A02 PIC3 A02
59 F_LVDS14_N F_LVDS9_P
DQ0- PIU10A059 PIJP10A21 A21 B21 PIJP10B21 NLF0LVDS90N PIR16A02 PIR17A02 COC32A
C32A COC33A
C33A
31 60 F_LVDS13_P F_LVDS9_N GND
PIU10A031 VBG DQ1+ PIU10A060 PIJP10A22 A22 B22 PIJP10B22
61
DQ1- PIU10A061
F_LVDS13_N NLF0LVDS0CK10P
F_LVDS_CK1_P
F_LVDS_CK1_N PIJP10A23 A23 B23 PIJP10B23
PIC32A01 PIC3 A01
65
DQ2+ PIU10A065
F_LVDS12_P NLF0LVDS0CK10N PIJP10A24 A24 B24 PIJP10B24
NLF0LVDS80N
F_LVDS8_N
C 66 F_LVDS12_N NLF0LVDS80P
F_LVDS8_P swap C
DQ2- PIU10A066 F_DX14 PIJP10A25 A25 B25 PIJP10B25
P3.3V_D P1.9VD 67 F_LVDS10_P NLF0DX14 GND
DQ3+ PIU10A067 PIJP10GND3 GND3 GND7 PIJP10GND7
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
68 F_LVDS10_N NLF0LVDS50P
F_LVDS5_P
DQ3- PIU10A068 PIJP10A26 A26 B26 PIJP10B26
PIC34A01 PIC35A01 DQ4+
69
PIU10A069 F_LVDS9_P swap
F_LVDS4_N
NLF0LVDS40N PIJP10A27 A27 B27 PIJP10B27
NLF0LVDS50N
F_LVDS5_N
COC34A
C34A COC35A
C35A 70 F_LVDS9_N
F_LVDS4_P
NLF0LVDS40P NLF0LVDS60N
F_LVDS6_N P1.9VD
DQ4- PIU10A070 PIJP10A28 A28 B28 PIJP10B28
PIC34A02 PIC35A02 71
DQ5+ PIU10A071
F_LVDS8_P F_LVDS1_P PIJP10A29 A29 B29 PIJP10B29
NLF0LVDS60P
F_LVDS6_P
72 F_LVDS8_N NLF0LVDS10P COU12A
U12A
COU13A DQ5- PIU10A072 F_LVDS1_N
NLF0LVDS10N PIJP10A30 A30 B30 PIJP10B30 NLF0LVDS30P
U13A 75 F_LVDS7_P F_LVDS3_P P2.3V 1 8
DQ6+ PIU10A075 PIJP10A31 A31 B31 PIJP10B31 NLF0LVDS30N COR18A
R18A PIU12A01 EN GND PIU12A08
GND 1 24 GND 76 F_LVDS7_N F_LVDS3_N swap 2 7
PIU13A01 VCCA VCCB PIU13A024 DQ6- PIU10A076 PIJP10A32 A32 B32 PIJP10B32 PIR18A01 PIR18A02 PIU12A02 IN GND PIU12A07
ballast to prevent spiking
F_LVDS2_N
2
PIU13A02 DIR
23
VCCB PIU13A023
77
DQ7+ PIU10A077
F_LVDS3_P NLF0LVDS20N
F_LVDS2_P PIJP10A33 A33 B33 PIJP10B33 88.7, 0.1% 3
PIU12A03 OUT
6
GND PIU12A06
SCLK F_DX14 3
PIU13A03 A1
22 78 F_LVDS3_N NLF0LVDS20P F_LVDS7_P
NLF0LVDS70P 4 5
OE PIU13A022 DQ7- PIU10A078 F_LVDSA_P PIJP10A34 A34 B34 PIJP10B34 PIU12A04 ADJ GND PIU12A05
SDATA F_DX15 4
PIU13A04 A2
21 F_LVDX14 SCLK NLF0LVDSA0P F_LVDS7_N
NLF0LVDS70N
B1 PIU13A021 F_LVDSA_N PIJP10A35 A35 B35 PIJP10B35
SCS F_DX7 5
PIU13A05 A3
20
B2 PIU13A020
F_LVDX15 SDATA 36
DQD0+ PIU10A036
NLF0LVDSA0N PIJP10GND4 GND4 GND8 PIJP10GND8 PIR19A01 MIC37122YM
10uF, 10V, X5R, 20%
10uF, 10V, X5R, 20%
PD F_DX12 6 19 F_LVDX7 SCS 37 NLF0DX15
F_DX15 COR19A
R19A PIR20A01
PIU13A06 A4 B3 PIU13A019 DQD0- PIU10A037 PIJP10A36 A36 B36 PIJP10B36 100, 1% COR20A
R20A
PDQ F_DX6 7 18 F_LVDX12 PD 38 NLF0DX7
F_DX7
PIU13A07 A5 B4 PIU13A018 DQD1+ PIU10A038 PIJP10A37 A37 B37 PIJP10B37
DCLK_RST F_DX13 8
PIU13A08 A6
17
B5 PIU13A017
F_LVDX6 PDQ 39
DQD1- PIU10A039 PIJP10A38 A38 B38 PIJP10B38
NLF0DX12
F_DX12 PIR19A02 100, 0.5% PIC36A02 PIC37A02 GND
9
PIU13A09 A7
16 F_LVDX13 DCLK_RST 43 NLF0DX6
F_DX6 PIR20A02 COC36A C37A
C36A COC37A
B6 PIU13A016 DQD2+ PIU10A043 PIJP10A39 A39 B39 PIJP10B39
10
PIU13A010 A8
15
B7 PIU13A015
44
DQD2- PIU10A044 PIJP10A40 A40 B40 PIJP10B40
NLF0DX13
F_DX13 PIC36A01 PIC37A01
11
PIU13A011 GND
14 45
B8 PIU13A014 DQD3+ PIU10A045
12
PIU13A012 GND
13 46 FX10A-80P/8-SV1(**)
GND PIU13A013 DQD3- PIU10A046
47 P5.0V_MAIN GND
SN74LVC8T245PWR
DQD4+ PIU10A047
48 ADC 1.9V LDOs
DQD4- PIU10A048
49
DQD5+ PIU10A049
mainboard connector
50
DQD5- PIU10A050 5.3mm +/- 0.2mm clearance
D 54 D
DQD6+ PIU10A054 Copyright 2013 Andrew "bunnie" Huang
55 COL10A
DQD6- PIU10A055 L10A
56 1PIL10A01 leaf header footprint Title
DQD7+ PIU10A056 Novena-AFE EVT1
GND GND 57
DQD7- PIU10A057 331051472057
ADC08D1020CIYB/NOPB COL11A
L11A Size Number Revision
1 PIL11A01
Copyrights: CC-BY-SA 3.0 B
ADC core Millmax 0990-3-50-20-75-14-11-0 Patents: Apache 2.0 Date: 5/4/2014 Sheet of
File: F:\largework\..\adc03.SchDoc Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6
P3.3V_CLK
COR10C
R10C NLF0LVDS0CK10P
F_LVDS_CK1_P
PIR10C01 PIR10C02
P3.3V_D 69.8, 1% PIR1 C02COR11C
A R11C COU10CB
U10CB P3.3V_CP A
0.01uF, 25V, X5R
PIC10C02
0.1uF, 6.3V, X5R
187, 1% 1
PIU10C01 4
COC10C COR12C
R12C VS VCP PIU10C04
PIR12C02 PIR1 C01 PIC12C01 PIC13C02
C10C COC11C
C11C PIR12C01
NLF0LVDS0CK10N
F_LVDS_CK1_N 11
PIU10C011 P3.3V_D
VS COC12C COC13C
PIC10C01 0.1uF, 6.3V, X5R PIC11C02 PIC11C01 69.8, 1% 12
PIU10C012
VS
27
VS_DRV PIU10C027
C12C C13C
32
PIU10C032
VS
35
VS_DRV PIU10C035
PIC12C02 PIC13C01
PIR13C01 PIR14C01
200, 1%
200, 1%
0.1uF, 6.3V, X5R 40 54
PIU10C040 VS VS_DRV PIU10C054
GND COC14C
C14C COU10CA
U10CA COR13C
R13C COR14C
R14C 41 46
PIU10C041 VS VS_DRV PIU10C046
13 56 49
COU11C PIC14C02 PIC14C01 PIU10C013 CLK OUT0(OUT0A) PIU10C056 PIR13C02 PIR14C02 PIU10C049 VS
U11C 14
PIU10C014 CLK
55 57 65
0.1uF, 6.3V, X5R OUT0(OUT0B) PIU10C055 PIU10C057 VS EP PIU10C065
PLL_PD PIU11C01
1 4 53 60 19
OE Vcc PIU11C04 OUT1(OUT1A) PIU10C053
1.0 GHz nom PIU10C060 VS GND PIU10C019
COC16C
C16C 52 61 59
OUT1(OUT1B) PIU10C052 NLFPGA0CLK0P
PIU10C061 VS GND PIU10C059
2 3 64 51 FPGA_CLK_P GND COC15C
C15C band 1:0.86-1.0GHz
PIU11C02 GNDOUT PIU11C03 PIC16C02 PIC16C01 PIU10C064 REFIN(REF1) OUT2(OUT2A) PIU10C051 NLFPGA0CLK0N NLADC0CLKIN0P
63 50 FPGA_CLK_N ADC_CLKIN_P band2: 0.573-0.75 GHz AD9520-3BCPZ
0.1uF, 25V, X5R
PIU10C063 REFIN(REF2) OUT2(OUT2B) PIU10C050 NLADC0CLKGEN0P
PIC15C02 PIC15C01
ASTX-H11-10.000MHZ-T 7
PIU10C07 48
PIU10C048 ADC_CLKGEN_P band3: 0.43-0.5625 GHz
REF_SEL OUT3(OUT3A)
0.1uF, 6.3V, X5R
TCXO - 2.5ppm 47 NLADC0CLKGEN0N
ADC_CLKGEN_N 4700pF 10% 50V X7R
OUT3(OUT3B) PIU10C047
PIC18C01 45
OUT4(OUT4A) PIU10C045
COC17C
C17C
COC18C NLDDC0SCL
C18CDDC_SCL 16 44 NLADC0CLKIN0N
ADC_CLKIN_N GND
PIU10C016 SCLK/SCL OUT4(OUT4B) PIU10C044 PIC17C02 PIC17C01
PIC18C02 NLDDC0SDA
DDC_SDA 17
PIU10C017 SDIO/SDA
43
OUT5(OUT5A) PIU10C043
GND 18 42 4700pF 10% 50V X7R
PIU10C018 SDO OUT5(OUT5B) PIU10C042 PIR15C01 PIR16C01
200, 1%
200, 1%
15
PIU10C015 CS
33
OUT6(OUT6A) PIU10C033 COR15C
R15C COR16C
R16C
GND 34 P3.7V
OUT6(OUT6B) PIU10C034
COU12C
21
PIU10C021 SP0
36 U12C
OUT7(OUT7A) PIU10C036
COJ13C
J13C 20
PIU10C020 SP1
37
OUT7(OUT7B) PIU10C037
PIR15C02 PIR16C02 PIU12C01 EN
16
BYP PIU12C06
38 2 5 P3.3V_CLK
B 1 PIJ13C01 OUT8(OUT8A) PIU10C038 PIU12C02 GND NC/ADJ PIU12C05 B
39 3 4
OUT8(OUT8B) PIU10C039 PIU12C03 VIN VOUT PIU12C04
10uF, 10V, X5R, 20%
test point (DNP) 8
PIU10C08 25 GND PAD
SYNC OUT9(OUT9A) PIU10C025 PIU12C0PAD PAD
0.1uF, 25V, X5R
10uF, 10V, X5R, 20%
int 30k PU + int POR 23
PIU10C023 RESET 26
OUT9(OUT9B) PIU10C026
NLPLL0PD
PLL_PD int 30k PU 24
PIU10C024 PD
28
OUT10(OUT10A) PIU10C028
MIC5319-3.3YML PIC19C02 PIC20C02
PIC21C02 COC19C COC20C
PIQ10C 3 29
OUT10(OUT10B) PIU10C029
C19C C20C
3
coordinate to ADC PD P3.3V_D 30
OUT11(OUT11A) PIU10C030
COC21C
C21C PIC19C01 PIC20C01
NLF0DX12
F_DX12 1 COQ10C
Q10C COR17C
R17C 22 31 PIC21C01
PIQ10C01 PIR17C02 PIR17C01 PIU10C022 EEPROM OUT11(OUT11B) PIU10C031
BSS138 DNP
COJ10C
J10C
PIQ10C2 58
PIU10C058 RSET
2
REFMON PIU10C02
NLPLL0REFMON
PLL_REFMON PIJ10C01 1
GND
2
GND
62 5 test point (DNP)
PIU10C062 CPRSET CP PIU10C05
COJ11C
J11C
GND 9 3 NLPLL0LD
PLL_LD
PIU10C09 LF LD PIU10C03 PIJ11C01 1
PLL_BYPASS 10 6 NLPLL0STAT
PLL_STAT test point (DNP) P3.7V COU13C
U13C P3.3V_CP
0.22uF, 10V, X5R, 10%
PIU10C010 BYPASS STATUS PIU10C06
10uF, 10V, X5R, 20%
PIR18C01 PIR19C01 COJ12C
J12C 1
PIU13C01 VIN
5
VOUT PIU13C05
0.1uF, 25V, X5R
R18C
COR18C R19C
COR19C AD9520-3BCPZ 2
4.12k, 1% 5.1k, 1%
PIJ12C01 1 PIC2 C02 PIU13C02 GND
PIC23C02
3 4
PIR18C02 PIR19C02 PIC24C02 COC22C
C22C
PIU13C03 ON/OFF N/C PIU13C04 COC23C
C23C
test point (DNP)
PLL_SP0
PLL_SP1
PIC24C01
COC24C
C24C
NLP 0SP NLP 0SP1 Default device ID = 0xB0
PIC2 C01 LP2980IM5-3.3/NOPB PIC23C01
PIR20C01 PIR21C01 GND GND
COR20C
R20C COR21C
R21C
C C
47k, 1% 47k, 1% Clockgen 3.3V LDOs
PIR20C02 PIR21C02
PLL_CP
GND
NLP L0CP
P3.3V_CLK
COR22C
R22C COR23C
R23C COR24C
R24C
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
NLPLL0LF
PLL_LF
1500pF, 50V, NP0, 5%
4.7uF, 6.3V, 20% X5R
PIR22C02 PIR22C01 PIR23C02 PIR23C01 PIR24C02 PIR24C01
0 ohm 3k, 1% 0 ohm PIC25C01 PIC26C01 PIC27C01 PIC28C01 PIC29C01 PIC30C01 PIC31C01 PIC32C01 PIC3 C01 PIC34C01
2200pF, 50V, X5R, 10%
COC25C
C25C COC26C
C26C COC27C
C27C COC28C
C28C COC29C
C29C COC30C
C30C COC31C
C31C COC32C
C32C COC33C
C33C COC34C
C34C
PIC25C02 PIC26C02 PIC27C02 PIC28C02 PIC29C02 PIC30C 2 PIC31C02 PIC32C02 PIC3 C02 PIC34C02
PIC35C02 PIC36C02 PIC37C01 PIC38C02
COC35C
C35C COC36C
C36C COC37C
C37C COC38C
C38C
DNP
PIC35C01 PIC36C01 PIC37C02 PIC38C01 GND
PIR25C01 Note: loop filter subject to adjustment P3.3V_D
COR25C
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
0.1uF, 6.3V, X5R
R25C
2.1k, 1% PIC39C01 PIC40C01 PIC41C01 PIC42C01
PIR25C02 C39C
COC39C C40C
COC40C C41C
COC41C C42C
COC42C
NLPLL0BYPASS
PLL_BYPASS PIC39C02 PIC40C02 PIC41C02 PIC42C02
GND
D Clock generator: Integer-N division from 1.72-2.25GHz VCO D
Copyright 2013 Andrew "bunnie" Huang
Title
Novena-AFE EVT1
Size Number Revision
Copyrights: CC-BY-SA 3.0 B
Patents: Apache 2.0 Date: 5/4/2014 Sheet of
File: F:\largework\..\clock02.SchDoc Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6
P5.5V COU10I
U10I
P3.3V_CMO Rules for connecting (or not connecting) to analog inputs:
10uF, 10V, X5R, 20%
1 5
PIU10I01 VIN VOUT PIU10I05
0.1uF, 25V, X5R
2 1. If VCMO is supported, it is okay to use DC coupling <-- typ case
PIU10I02 GND
PIC10I 2 COC10I 3
PIU10I03 4
ON/OFF N/C PIU10I04
PIC1 I02 COC11I
C10I C11I 2. If AC coupling is used, VCMO must be grounded on the probe side
A PIC10I01 LP2980IM5-3.3/NOPB PIC1 I01 A
3. If one channel is AC coupled, and an input pair is unused, tie VCMO to ground, and tie unused inputs to an AC ground (e.g. capacitors to ground)
Use termination plugs to tie unused inputs to VCMO (not GND)
GND GND 4. If one channel is DC coupled, and an input pair is unused, tie unused inputs to VCMO directly <-- typ case
P3.3V_CMO
P12.0V
PIU1I08 P5.5V
8
COJP10I
JP10I COU11IA
U11IA
1 2 LMV358IPT (ST AVL only) COP12I
P12I
GND PIJP10I01 NLVIN0A0N
PIU11I02
2 VIN_A_N 1 DDC_SCL DDC_SDA
A+ PIJP10I02 NLVIN0A0P NLADC0VCMO
PIU11I01 PIP12I01 1 2 PIP12I02 NLVCMO0A
3 VIN_A_P ADC_VCMO 3 (power down) F_DX12 VCMO_A
A- PIJP10I03 PIU11I03 COR10I
R10I
PIP12I03 3 4 PIP12I04
4 VCMO_A
GND PIJP10I04 PIR10I01 PIR10I02 PIP12I05
5 6 PIP12I06
5
B- PIJP10I05
NLF0LVDSA0N
F_LVDSA_N
PIU1 I04 0 ohm PIP12I07 7 8 PIP12I08
4
6 NLF0LVDSA0P
F_LVDSA_P trigger A
B+ PIJP10I06
7 4x2 2.54mm male header, shrouded, e.g. FCI 75869-132 or equiv
GND PIJP10I07
MOLEX 678005025 GND
N12.0V header contact rated to 3A
GND plug rated 1A, 0.015 ohm
P3.3V_CMO wire is 28 awg, 7-strands, 212 mOhm/m
B P12.0V B
COJP11I
JP11I
PIU1 I08 P5.5V bulk of ground return current
8
1 COU11IB
U11IB comes through SATA cable
GND PIJP11I01 NLVIN0B0N LMV358IPT (ST AVL only) COP13I
2 VIN_B_N 6 P13I
A+ PIJP11I02 NLVIN0B0P
PIU11I06
NLDDC0SCL NLDDC0SDA
3 VIN_B_P 7 DDC_SCL DDC_SDA
A- PIJP11I03 PIU11I07
NLF0DX12 PIP13I01 1 2 PIP13I02 NLVCMO0B
4 5 (power down) F_DX12 VCMO_B
GND PIJP11I04 NLF0LVDSB0N PIU11I05 COR11I
R11I PIP13I03 3 4 PIP13I04
5 F_LVDSB_N VCMO_B
B- PIJP11I05 PIR11I01 PIR11I02 PIP13I05 5 6 PIP13I06
6
B+ PIJP11I06
NLF0LVDSB0P
F_LVDSB_P trigger B
PIU1 I04 0 ohm PIP13I07 7 8 PIP13I08
4
7
GND PIJP11I07
4x2 2.54mm male header, shrouded, e.g. FCI 75869-132 or equiv
MOLEX 678005025
GND
N12.0V
GND
GND common-mode offset buffers High speed analog power headers
High speed analog signal headers
C C
P3.3V_D
P3.3V_D
Device addr = 0xA4
0.1uF, 6.3V, X5R
PIC12I01 COU12I
U12I
COC12I
C12I 1 8
PIU12I01 A0 VCC PIU12I08
PIC12I02 2
PIU12I02 A1
7
WP PIU12I07
3
PIU12I03 A2
6 DDC_SCL
SCL PIU12I06
4 5
PIU12I04 GND SDA PIU12I05
DDC_SDA
D GND D
24LC32A-I/ST Copyright 2013 Andrew "bunnie" Huang
Title
Novena-AFE EVT1
GND GND
Size Number Revision
ID & cal record EEPROM, 4kx8 Copyrights: CC-BY-SA 3.0 B
Patents: Apache 2.0 Date: 5/4/2014 Sheet of
File: F:\largework\..\connect04.SchDoc Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6
note: these are not for termination, they are for over-voltage protection
P5.0V_MAIN
COU10D
U10D
A TRIG_LEVEL 1
PIU10D01 8 P4.5V_TRIG A
NLDIG0IN0 COR10D
R10D +INA V+ PIU10D08 NLF0DX5
DIG_IN0 PIR10D01 PIR10D02 2
PIU10D02 7 F_DX5
-INA OUTA PIU10D07 NLF0DX4 i Z0
49.9, 1% 3
PIU10D03 6
PIU10D06 F_DX4
NLDIG0IN1 COR11D
R11D +INB OUTB i Z0
DIG_IN1 PIR11D01 PIR11D02 4
PIU10D04 5
-INB V- PIU10D05 COU11D
49.9, 1% U11D
TLV3502AIDCNT NLDDC0SCL
DDC_SCL 3 8 NLTRIG0LEVEL
TRIG_LEVEL
NLDDC0SDA PIU11D03 SCL VOUT PIU11D08
DDC_SDA 4
PIU11D04 SDA
8
7
6
5
PIRP10D 8 PIRP10D 7 PIRP10D 6 PIRP10D 5 PIR12D02
1M 5% 0402x4 rpack
7
VREF PIU11D07
10uF, 10V, X5R, 20%
6 COR12D
R12D
VA PIU11D06
0.1uF, 25V, X5R
0.1uF, 25V, X5R
FLOAT_LEVEL 1 10k, 1%
PIU11D01 ADR0
PIC10D 2 COC10D PIC1 D02 COC11D PIC12D02 COC12D PIR12D01
RP10D
CORP10D C10D C11D C12D
2
PIU11D02 ADR1 GND
5
PIU11D05
NLFLOAT0LEVEL
FLOAT_LEVEL
PIRP10D 1 PIRP10D 2 PIRP10D 3 PIRP10D 4 PIC10D01 PIC1 D01 PIC12D01 DAC101C085CIMM/NOPB PIR13D02 guarantees floating inputs default to 0
1
2
3
4
GND COR13D
R13D
COU12D
U12D Trigger DAC = 0x14 10k, 1%
COR14D
1
PIU12D01
+INA
8
V+ PIU12D08
PIR13D01
NLDIG0IN2
DIG_IN2 R14D 2 7 NLF0DX8
F_DX8
PIR14D01 PIR14D02 PIU12D02 -INA OUTA PIU12D07 i Z0
3 6 NLF0DX16
F_DX16
NLDIG0IN3
DIG_IN3 COR15D 49.9, 1%
R15D PIU12D03 +INB
4
OUTB PIU12D06
5
i Z0
PIR15D01 PIR15D02 PIU12D04 -INB V- PIU12D05
49.9, 1% TRIG_LEVEL GND
TLV3502AIDCNT
P5.0V_MAIN
COP10D
P10D
B DIG_IN0 P5.5V COU13D
U13D P4.5V_TRIG B
PIP10D01 1 2 PIP10D02
10uF, 10V, X5R, 20%
PIP10D03 DIG_IN1 COU14D
U14D 1 5
3 4 PIP10D04 PIU13D01 VIN VOUT PIU13D05
0.1uF, 25V, X5R
0.1uF, 25V, X5R
PIP10D05 5 DIG_IN2 TRIG_LEVEL 1 8 2
6 PIP10D06 COR16D
R16D
PIU14D01 +INA V+ PIU14D08 PIU13D02 GND
PIP10D07 7 8 PIP10D08
DIG_IN3 NLDIG0IN4
DIG_IN4 PIR16D01 PIR16D02 2
PIU14D02 7
-INA OUTA PIU14D07
NLF0DX0
F_DX0
i Z0
PIC13D02 3
PIU13D03 4
ON/OFF N/C PIU13D04
PIC14D02 PIC15D02
PIP10D09 9
DIG_IN4 49.9, 1% 3 6 NLF0DX3
F_DX3 COC13D
C13D COC14D
C14D COC15D
C15D
10 PIP10D010 NLDIG0IN5 COR17D
R17D PIU14D03 +INB OUTB PIU14D06 i Z0 PIC13D01 PIC14D01 PIC15D01
PIP10D011 11
DIG_IN5 DIG_IN5 4 5 LP2980IM5-4.5/NOPB
12 PIP10D012 PIR17D01 PIR17D02 PIU14D04 -INB V- PIU14D05
PIP10D013 13
DIG_IN6 49.9, 1%
14 PIP10D014
PIP10D015 15
DIG_IN7 TLV3502AIDCNT if 4.5V reg is not available, 4.7V can work too
16 PIP10D016
PIP10D017 17
DIG_IN8 GND voltage set low to have I2C work with no level shifters GND
18 PIP10D018
8
7
6
5
PIRP1 D08 PIRP1 D07 PIRP1 D06 PIRP1 D05
1M 5% 0402x4 rpack
PIP10D019 19
DIG_IN9 4.5V * 0.7V = 3.15V VIH
20 PIP10D020
10uF, 10V, X5R, 20%
0.1uF, 25V, X5R
0.1uF, 25V, X5R
Header 10X2 FLOAT_LEVEL
RP11D
CORP1 D PIC16D02 PIC17D02 PIC18D02
COC16D
C16D COC17D
C17D COC18D
C18D
PIRP1 D01 PIRP1 D02 PIRP1 D03 PIRP1 D04 PIC16D01 PIC17D01 PIC18D01
1
2
3
4
GND GND
COU15D
U15D
1 8
NLDIG0IN6 COR18D
R18D PIU15D01 +INA V+ PIU15D08 NLF0DX2
DIG_IN6 2 7 F_DX2
PIR18D01 PIR18D02 PIU15D02 -INA OUTA PIU15D07 NLF0DX11 i Z0
3 6 F_DX11
NLDIG0IN7
DIG_IN7 COR19D 49.9, 1%
R19D PIU15D03 +INB
4
OUTB PIU15D06
5
i Z0
PIR19D01 PIR19D02 PIU15D04 -INB V- PIU15D05
49.9, 1% TRIG_LEVEL
TLV3502AIDCNT
C C
P5.0V_MAIN
COU16D
U16D
TRIG_LEVEL 1
PIU16D01 +INA
8
NLDIG0IN8 COR20D
R20D V+ PIU16D08 NLF0DX1
DIG_IN8 2
PIU16D02 -INA
7 F_DX1
PIR20D01 PIR20D02 OUTA PIU16D07 NLF0DX17 i Z0
3 6 F_DX17
NLDIG0IN9
DIG_IN9 COR21D 49.9, 1%
R21D PIU16D03 +INB
4
OUTB PIU16D06
5
i Z0
PIR21D01 PIR21D02 PIU16D04 -INB V- PIU16D05
49.9, 1%
TLV3502AIDCNT
COR22D
R22D
10uF, 10V, X5R, 20%
PIR22D01 PIR22D02
0.1uF, 25V, X5R
1M, 1%
FLOAT_LEVEL PIC19D02 PIC20D02
R23D
COR23D C19D
COC19D C20D
COC20D
PIR23D01 PIR23D02
1M, 1% PIC19D01 PIC20D01
GND
LA digital input comparators
0-5V range
D D
adjustable threshold Copyright 2013 Andrew "bunnie" Huang
Title
100 MHz peak recommended speed Novena-AFE EVT1
1M input impedance Size Number Revision
Copyrights: CC-BY-SA 3.0 B
Patents: Apache 2.0 Date: 5/4/2014 Sheet of
File: F:\largework\..\digital05.SchDoc Drawn By:
1 2 3 4 5 6
1 2 3 4 5 6
2.3V 3% @ 1.5A pre-regulator for ADC 2.3V to 1.9V/1.8V via LDO COL10P
L10P
P5.0V_MAIN 5.7V 3.5% @ 1A pre-boost for 5V analog LDO
P5.0V_MAIN COD10P
D10P P5.5V
COR10P COR11P PIL10P01 PIL10P02
PIR12P02 R10P
PIR10P02 PIR10P01
R11P
PIR11P02 PIR11P01 2.2uH, coilcraft MSS5131-222ML 1
PID10P01 2
PID10P02 5.735V nom voltage budget: COM10P
M10P
COR12P
R12P P2.3V
10k, 1% 28.7k, 1% COR13P 1 PIM10P01
10uF, 10V, X5R, 20%
10uF, 10V, X5R, 20%
10k, 1% 2.322V nom R13P COU10P
U10P CDBMT240-HF 5V target
actually M2.5; fix libref
PIR13P02 PIR13P01
A PIR12P01 GND 10k, 1% 1
PIU10P01 PGND
6
SW PIU10P06
0.2V drop-out MIC5319 M2 mounting hole A
10uF, 10V, X5R, 20%
COU11P
U11P 2
PIU10P02 VIN
5
AGND PIU10P05 COR14P
PIC10P02 PIC1 P02 0.05V accurancy MIC5319 COM11P
M11P
6 1 3 4 R14P COC10P
C10P COC11P
C11P 0.12V LMR62421 accuracy
PIU11P06 EN FB PIU11P01 COL11P
L11P PIU10P03 EN FB PIU10P04 PIR14P02 PIR14P01 1 PIM11P01
5
PIU11P05
VINA
2
GND PIU11P02
PIC12P02 7
PAD PIU10P07 35.7k, 0.1% PIC10P01 PIC1 P01 0.06V resistor accuracy
4 3 COC12P
C12P COC13P
C13P 0.2V I-V drop 1m power line M2 mounting hole
PIU11P04
VIND SW PIU11P03 PIL11P01 PIL11P02
PIC12P01
10uF, 10V, X5R, 20%
22uF, 6.3V, X5R, 20%
22uF, 6.3V, X5R, 20%
7 2.2uH, coilcraft MSS5131-222ML LMR62421XSDE/NOPB 0.1V I-V drop 1m ground line COM12P
M12P
GND PIU11P07 PIC14P01 PIC15P01 PIC13P01 PIC13P02
PIC16P02 LMR10520YSDE
2 PID1 P02 COD11P COC14P
C14P COC15P
C15P PIR15P01 680pF 5% NP0 50V
5.73V starting voltage
1 PIM12P01
COC16P
C16P D11P PIC14P02 PIC15P02 COR15P
R15P GND M2 mounting hole
PIC16P01
PID1P01 CDBMT240-HF
PIR15P02
10k, 0.5% COM13P
M13P
1
1 PIM13P01
GND
GND GND M2 mounting hole
GND
GND
3.7V @ 1.5A to LDO to 3.3V Digital usage expected to be ~10-100mA COL12P
L12P
11.8V 3.5% @ 0.2A pre-boost for 10V analog LDO GND
P5.0V_MAIN
P5.0V_MAIN COD12P
D12P P12.0V
COR16P COR17P PIL12P01 PIL12P02
PIR18P02 R16P
PIR16P02 PIR16P01
R17P
PIR17P02 PIR17P01 15uH LPS4018-153MLB 1 2
PID12P01 PID12P02
11.86V nom
COR18P
R18P P3.7V
10k, 1% 52.3k, 1% COR19P
22uF, 25V, X5R, 10%
10k, 1% 3.738V nom R19P COU12P
U12P CDBMT240-HF
PIR19P02 PIR19P01
B PIR18P01 GND 1 6 B
10k, 1% PIU12P01 PGND SW PIU12P06
10uF, 10V, X5R, 20%
COU13P
U13P 2
PIU12P02 VIN
5
AGND PIU12P05 COR20P
PIC17P01
0.1uF, 25V, X5R
6 1 3 4 R20P COC17P
C17P
PIU13P06 EN FB PIU13P01 COL13P
L13P PIU12P03 EN FB PIU12P04 PIR20P02 PIR20P01
5
PIU13P05 VINA
2
GND PIU13P02
PIC18P02 PIC32P02 7
PAD PIU12P07 84.5k, 1% PIC17P02
4
PIU13P04 VIND
3 COC18P
C18P COC32P
C32P COC19P
C19P
SW PIU13P03 PIL13P01 PIL13P02
10uF, 10V, X5R, 20%
PIC18P01 PIC32P01
22uF, 6.3V, X5R, 20%
22uF, 6.3V, X5R, 20%
7 2.2uH, coilcraft MSS5131-222ML LMR62421XSDE/NOPB
GND PIU13P07 PIC20P01 PIC21P01 PIC19P01 PIC19P02
PID13P02 COD13P
2
PIC2 P02 LMR10520YSDE COC20P
C20P COC21P
C21P PIR21P01 270pF 5% NP0 50V
COC22P
C22P D13P PIC20P02 PIC21P02 COR21P
R21P GND
PIC2 P01 PID13P01 CDBMT240-HF 10k, 1%
1
PIR21P02
GND
GND GND
GND
GND
GND
COL14P
L14P
22uF, 25V, X5R, 10%
PIL14P01 PIL14P02
-12V 4% @ 0.15A for -10V analog LDO 6.8uH LPS4018-682MLB
C PIC23P01 3.3V LDO for misc digital functions C
(make plans for lower-voltage config too) COD14P
D14P COC23P
C23P
2
PID14P02 1
PID14P01 PIC23P02
P5.0V_MAIN COU14P
U14P I2C address map:
10uF, 10V, X5R, 20%
5 6 CDBMT240-HF P3.7V
4700pF 10% 50V X7R
PIU14P05 IN SW PIU14P06 COU15P Trigger DAC = 0x14
8 -12.03V nom U15P
OUT PIU14P08
PIC24P02 PIR2 P01 1
PIU15P01 EN
6
BYP PIU15P06
COC24P
C24P 1
PIU14P01 COMP FB
9
PIU14P09
COR22P
R22P N12.0V 2 5
PIU15P02 GND NC/ADJ PIU15P05
P3.3V_D ADC EEPROM = 0xA4
PIC24P01 PIC25P02 100k, 1% 3
PIU15P03 VIN
4
VOUT PIU15P04
COR23P COR24P COC26PPIR2 P02 Clock generator = 0xB0
10uF, 10V, X5R, 20%
COC25P
C25P 10 R23P R24P C26P PAD
VREF PIU14P010 PIU15P0PAD PAD
0.1uF, 25V, X5R
PIR23P02 PIR23P01
PIR24P02 PIR24P01
PIC25P01
10uF, 10V, X5R, 20%
121k, 1% 1.2M, 1% PIC26P01 PIC26P02
Connected on mainboard:
4
PIU14P04 EN
11
PP PIU14P011
MIC5319-3.3YML PIC27P02 PIC28P02 HDMI DDC (0xA0, 0x74, 0x6E, 0x88, 0x94, 0x96)
2 PIC29P02 10pF 5% NP0 50V PIC30P02 COC27P
C27P COC28P
C28P PMIC (0x10)
COR25P
R25P GND PIU14P02 COC29P COC30P
PIR25P02 PIR25P01 3
PIU14P03 VIN
7
PS_GND PIU14P07
C29P C30P PIC27P01 PIC28P01
10.0, 1% PIC29P01 0.22uF, 10V, X5R, 10% PIC30P01
TPS63700DRCTG4
GND (p) Analog Trigger DAC = 0x9A
PIC31P02 GND
COC31P
C31P (p) Probe EEPROM = 0xA6
PIC31P01 0.1uF, 25V, X5R
GND (p) Analog Trim DAC = 0x9C
GND
D D
Copyright 2013 Andrew "bunnie" Huang
Title
Novena-AFE EVT1
Size Number Revision
Copyrights: CC-BY-SA 3.0 B
Patents: Apache 2.0 Date: 5/4/2014 Sheet of
File: F:\largework\..\power01.SchDoc Drawn By:
1 2 3 4 5 6