DOKK / manpages / debian 10 / alliance / GENLIB_LORES.3.en
GENLIB_LORES.3(August 16, 2002) GENLIB_LORES.3(August 16, 2002)

GENLIB_LORES - add a logical resistor to the current netlist figure

#include <genlib.h>
void GENLIB_LORES(type,resi,rcon1,rcon1,name)
char type ;
double resi ;
char ∗rcon1, ∗rcon1 ;
char ∗name ;

See the file buster/alliance/alc_origin.1.en.gz.

Type of the resistor to be created in the current figure
Resistance value.
Name of the signals on which the given resistor connectors are to be linked.
Resistor name. The unicity of the name is not checked.

LORES adds a logical resistor to the current working figure. This resistor has each of its pin logicaly linked to the adequat signal given as parameter. For the time being, the type attribut may take the following value:

for a MIM (metal) type resistor.

"GENLIB_LORES impossible : missing GENLIB_DEF_LOFIG"

No figure has been yet specified by a call to DEF_LOFIG. So it isn't possible to add anything. you must call DEF_LOFIG before any other netlist call.

#include <genlib.h>
int main(int argc,char ∗argv[])
{

/∗ Create a figure to work on, a parallel resistor ∗/
GENLIB_DEF_LOFIG("parallel_res") ;
/∗ Define interface ∗/
GENLIB_LOCON("i",IN,"input") ;
GENLIB_LOCON("f",OUT,"output") ;
/∗ Add resistors ∗/
GENLIB_LORES(RESMIM,5.1,"input","output","res1") ;
GENLIB_LORES(RESMIM,5.2,"input","output","res2") ;
/∗ Save all that on disk ∗/
GENLIB_SAVE_LOFIG() ;
return 0 ; }

genlib(1), GENLIB_BUS(3), GENLIB_ELM(3), GENLIB_LOINS(3), GENLIB_LOCON(3).

See the file buster/alliance/alc_bug_report.1.en.gz.

ASIM/LIP6 PROCEDURAL GENERATION LANGUAGE