LOON(1) | CAO-VLSI Reference Manual | LOON(1) |
See the file buster/alliance/alc_origin.1.en.gz.
loon is a CAD tool that allows to remove fanout problems within a gate netlist and also to optimize the delay. The netlist can be hierarchical and is flattened if necessary. loon runs in batch mode and a parameter file can be used (see man lax) to parametrize optimization by adding informations on outputs (fanin), inputs (fanout, delay) and by setting general parameters such as optimization level. loon permits to compute delays of gates in the netlist and gives the critical path in the netlist. The global optimization of loon performs gate repowering to decrease the critical path delay and global capacitance. Buffers are only inserted in critical path.
lax Parameter file description
The lax file is common with other logic synthesis tools and is used for
driving the synthesis process. See lax(5) manual for more
detail.
lax uses a lot of parameters to guide every step of the synthesis process. Some parameters are globally used (for example, optimization level whereas others are specifically used (load capacitance for the netlist optimization only). Here is the default lax file (see the user's manual for further information about the syntax of the '.lax' file):
Optimization mode = 2 (50% area - 50% delay)
Input impedance = 0
Output capacitance = 0
Delayed input = none
Auxiliary signal saved = none
The following environment variables have to be set before using loon :
MBK_CATA_LIB gives the auxiliary paths of the directories of input files (behavioural description).
MBK_TARGET_LIB gives the path (single) of the directory of the selected standard cell library.
MBK_IN_LO gives the input format of the structural description.
MBK_OUT_LO gives the output format of the structural description.
You can call loon as follows :
loon alu alu_loon
loon(1), boog(1), boom(1), lax(5), vbe(5), proof(1), asimut(1), vhdl(5), ocp(1), nero(1), sxlib(5).
See the file buster/alliance/alc_bug_report.1.en.gz.
Sept 01 2000 | ASIM/LIP6 |