| OPENSSL_IA32CAP(3SSL) | OpenSSL | OPENSSL_IA32CAP(3SSL) |
OPENSSL_ia32cap - the x86[_64] processor capabilities vector
env OPENSSL_ia32cap=... <application>
OpenSSL supports a range of x86[_64] instruction set extensions. These extensions are denoted by individual bits in capability vector returned by processor in EDX:ECX register pair after executing CPUID instruction with EAX=1 input value (see Intel Application Note #241618). This vector is copied to memory upon toolkit initialization and used to choose between different code paths to provide optimal performance across wide range of processors. For the moment of this writing following bits are significant:
For example, in 32-bit application context clearing bit #26 at run-time disables high-performance SSE2 code present in the crypto library, while clearing bit #24 disables SSE2 code operating on 128-bit XMM register bank. You might have to do the latter if target OpenSSL application is executed on SSE2 capable CPU, but under control of OS that does not enable XMM registers. Historically address of the capability vector copy was exposed to application through OPENSSL_ia32cap_loc(), but not anymore. Now the only way to affect the capability detection is to set OPENSSL_ia32cap environment variable prior target application start. To give a specific example, on Intel P4 processor 'env OPENSSL_ia32cap=0x16980010 apps/openssl', or better yet 'env OPENSSL_ia32cap=~0x1000000 apps/openssl' would achieve the desired effect. Alternatively you can reconfigure the toolkit with no-sse2 option and recompile.
Less intuitive is clearing bit #28, or ~0x10000000 in the "environment variable" terms. The truth is that it's not copied from CPUID output verbatim, but is adjusted to reflect whether or not the data cache is actually shared between logical cores. This in turn affects the decision on whether or not expensive countermeasures against cache-timing attacks are applied, most notably in AES assembler module.
The capability vector is further extended with EBX value returned by CPUID with EAX=7 and ECX=0 as input. Following bits are significant:
To control this extended capability word use ':' as delimiter when setting up OPENSSL_ia32cap environment variable. For example assigning ':~0x20' would disable AVX2 code paths, and ':0' - all post-AVX extensions.
It should be noted that whether or not some of the most "fancy" extension code paths are actually assembled depends on current assembler version. Base minimum of AES-NI/PCLMULQDQ, SSSE3 and SHA extension code paths are always assembled. Apart from that, minimum assembler version requirements are summarized in below table:
Extension | GNU as | nasm | llvm ------------+--------+--------+-------- AVX | 2.19 | 2.09 | 3.0 AVX2 | 2.22 | 2.10 | 3.1 ADCX/ADOX | 2.23 | 2.10 | 3.3 AVX512 | 2.25 | 2.11.8 | see NOTES AVX512IFMA | 2.26 | 2.11.8 | see NOTES VAES | 2.30 | 2.13.3 |
Even though AVX512 support was implemented in llvm 3.6, compilation of assembly modules apparently requires explicit -march flag. But then compiler generates processor-specific code, which in turn contradicts the mere idea of run-time switch execution facilitated by the variable in question. Till the limitation is lifted, it's possible to work around the problem by making build procedure use following script:
#!/bin/sh exec clang -no-integrated-as "$@"
instead of real clang. In which case it doesn't matter which clang version is used, as it is GNU assembler version that will be checked.
Not available.
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Licensed under the OpenSSL license (the "License"). You may not use this file except in compliance with the License. You can obtain a copy in the file LICENSE in the source distribution or at <https://www.openssl.org/source/license.html>.
| 2022-06-24 | 1.1.1n |