| libnvme(2) | API Manual | libnvme(2) |
enum nvme_register_offsets - controller registers for all transports. This is the layout of BAR0/1 for PCIe, and properties for fabrics.
enum nvme_register_offsets {
NVME_REG_CAP ,
NVME_REG_VS ,
NVME_REG_INTMS ,
NVME_REG_INTMC ,
NVME_REG_CC ,
NVME_REG_CSTS ,
NVME_REG_NSSR ,
NVME_REG_AQA ,
NVME_REG_ASQ ,
NVME_REG_ACQ ,
NVME_REG_CMBLOC ,
NVME_REG_CMBSZ ,
NVME_REG_BPINFO ,
NVME_REG_BPRSEL ,
NVME_REG_BPMBL ,
NVME_REG_CMBMSC ,
NVME_REG_CMBSTS ,
NVME_REG_CRTO ,
NVME_REG_PMRCAP ,
NVME_REG_PMRCTL ,
NVME_REG_PMRSTS ,
NVME_REG_PMREBS ,
NVME_REG_PMRSWTP ,
NVME_REG_PMRMSCL ,
NVME_REG_PMRMSCU
};
| enum nvme_register_offsets | April 2024 |