srec_intel(5) | File Formats Manual | srec_intel(5) |
srec_intel - Intel Hexadecimal object file format specification
This format is also known as the Intel MCS‐86 Object format.
This document describes the hexadecimal object file format for the Intel 8‐bit, 16‐bit, and 32‐bit microprocessors. The hexadecimal format is suitable as input to PROM programmers or hardware emulators.
Hexadecimal object file format is a way of representing an absolute binary object file in ASCII. Because the file is in ASCII instead of binary, it is possible to store the file is non‐binary medium such as paper‐tape, punch cards, etc.; and the file can also be displayed on CRT terminals, line printers, etc.. The 8‐bit hexadecimal object file format allows for the placement of code and data within the 16‐bit linear address space of the Intel 8‐bit processors. The 16‐bit hexadecimal format allows for the 20‐bit segmented address space of the Intel 16‐bit processors. And the 32‐bit format allows for the 32‐bit linear address space of the Intel 32‐bit processors.
--address-length=2 | “i8hex” | 16‐bit | |
--address-length=3 | “i16hex” | 20‐bit | segmented |
--address-length=4 | “i32hex” | 32‐bit | linear |
The hexadecimal representation of binary is coded in ASCII alphanumeric characters. For example, the 8‐bit binary value 0011‐1111 is 3F in hexadecimal. To code this in ASCII, one 8‐bit byte containing the ASCII code for the character '3' (0011‐0011 or 0x33) and one 8‐bit byte containing the) ASCII code for the character 'F' (0100‐0110 or 0x46) are required. For each byte value, the high‐order hexadecimal digit is always the first digit of the pair of hexadecimal digits. This representation (ASCII hexadecimal) requires twice as many bytes as the binary representation.
A hexadecimal object file is blocked into records, each of which contains the record type, length, memory load address and checksum in addition to the data. There are currently six (6) different types of records that are defined, not all combinations of these records are meaningful, however. The record are:
Record Mark | Record Length | Load Offset | Record Type | Data | Check sum |
(32‐bit format only)
Record Mark (“:”) | Record Length (2) | Load Offset (0) | Record Type (4) | ULBA (2 bytes) | Check sum |
The 32‐bit Extended Linear Address Record is used to specify bits 16‐31 of the Linear Base Address (LBA), where bits 0‐15 of the LBA are zero. Bits 16‐31 of the LBA are referred to as the Upper Linear Base Address (ULBA). The absolute memory address of a content byte in a subsequent Data Record is) obtained by adding the LBA to an offset calculated by adding the Load Offset field of the containing Data Record to the index of the byte in the Data Record (0, 1, 2, ... n). This offset addition is done) modulo 4G (i.e. 32‐bits from 0xFFFFFFFF to 0x00000000) results in wrapping around from the end to the beginning of the 4G linear address defined by the LBA. The linear address at which a particular byte is loaded is calculated as:
(16‐ or 32‐bit formats)
Record Mark (“:”) | Record Length (2) | Load Offset (0) | Record Type (2) | USBA (2 bytes) | Check sum |
The 16‐bit Extended Segment Address Record is used to specify bits 4‐19 of the Segment Base Address (SBA), where bits 0‐3 of the SBA are zero. Bits 4‐19 of the SBA are referred to as the Upper Segment Base Address (USBA). The absolute memory address of a content byte in a subsequent Data Record is) obtained by adding the SBA to an offset calculated by adding the Load Offset field of the containing Data Record to the index of the byte in the Data Record (0, 1, 2, ... n). This offset addition is done modulo 64K (i.e. 16‐bits from 0xFFFF to 0x0000 results in wrapping around from the end to the beginning of the 64K segment defined by the SBA. The address at which a particular byte is loaded is calculated as:
When an Extended Segment Address Record defines the value of SBA, it may appear anywhere within a 16‐bit hexadecimal object file. This value remains in effect until another Extended Segment Address Record is encountered. The SBA defaults to zero until an Extended Segment Address Record is encountered.
The contents of the individual fields within the record are:
(8‐, 16‐ or 32‐bit formats)
Record Mark (“:”) | Record Length | Load Offset | Record Type | Data | Check sum |
The Data Record provides a set of hexadecimal digits that represent the ASCII code for data bytes that make up a portion of a memory image. The method for calculating the absolute address (linear in the 8‐bit and 32‐bit case and segmented in the 16‐bit case) for each byte of data is described in the discussions of the Extended Linear Address Record and the Extended Segment Address Record.
The contents of the individual fields within the record are:
Note: Care must be taken when the addresses with an record span the end of addressing. The behaviour is different for linear and segmented addressing modes.
The srec_cat(1) program will never output records such as these, it will always produce separate records on output.
(32‐bit format only)
Record Mark (“:”) | Record Length (4) | Load. Offset (0) | Record Type (5) | EIP (4 bytes) | Check sum |
The Start Linear Address Record is used to specify the execution start address for the object file. The value given is the 32‐bit linear address for the EIP register. Note that this record only specifies the code address within the 32‐bit linear address space of the 80386. If the code is to start execution in the real mode of the 80386, then the Start Segment Address Record should be used instead, since that record specifies both the CS and IP register contents necessary for real mode.
The Start Linear Address Record can appear anywhere in a 32‐bit hexadecimal object file. If such a record is not present in a hexadecimal object file, a loader is free to assign a default execution start address.
The contents of the individual fields within the record are:
(16‐ or 32‐bit formats)
Record Mark (“:”) | Record Length (4) | Load. Offset (0) | Record Type (3) | CS (2 bytes) | IP (2 bytes) | Check sum |
The Start Segment Address Record is used to specify the execution start address for the object file. The value given is the 20‐bit segment address for the CS and IP registers. Note that this record only specifies the code address within the 20‐bit segmented address space of the 8086/80186. The Start Segment Address Record can appear anywhere in a 16‐bit hexadecimal object file. If such a record is not present in a hexadecimal object file, a loader is free to assign a default start address.
The contents of the individual fields within the record are:
(8‐, 16‐, or 32‐bit formats)
Record Mark (“:”) | Record Length (0) | Load Offset (0) | Record Type (1) | Check sum (0xFF) |
The End of File Record specifies the end of the hexadecimal object file.
The contents of the individual fields within the record are:
In general, binary data will expand in sized by approximately 2.3 times when represented with this format.
Here is an example Intel hex file. It contains the data “Hello, World” to be loaded at address 0.
:0D00000048656C6C6F2C20576F726C640AA1 :00000001FF
This information comes (very indirectly) from Microprocessors and Programmed Logic, Second Edition, Kenneth L. Short, 1987, Prentice‐Hall, ISBN 0‐13‐580606‐2.
http://en.wikipedia.org/wiki/Intel_HEX
srec_cat version 1.64
Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
2008, 2009, 2010, 2011, 2012, 2013, 2014 Peter Miller
The srec_cat program comes with ABSOLUTELY NO WARRANTY; for
details use the 'srec_cat -VERSion License' command. This is free
software and you are welcome to redistribute it under certain conditions;
for details use the 'srec_cat -VERSion License' command.
Scott Finneran | E‐Mail: | scottfinneran@yahoo.com.au |
Peter Miller | E‐Mail: | pmiller@opensource.org.au |
This manual page is derived from a file marked as follows:
Intel Hexadecimal Object File Format Specification; Revision A, 1/6/88
Disclaimer: Intel makes no representation or warranties with respect to the contents hereof and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, Intel reserves the right to revise this publication from time to time in the content hereof without obligation of Intel to notify any person of such revision or changes. The publication of this specification should not be construed as a commitment on Intel's part to implement any product.
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